James Hogan 310e3f0a1d target/mips: Fix TLBWI shadow flush for EHINV,XI,RI ... Writing specific TLB entries with TLBWI flushes shadow TLB entries unless an existing entry is having its access permissions upgraded. This is necessary as software would from then on expect the previous mapping in that entry to no longer be in effect (even if QEMU has quietly evicted it to the shadow TLB on a TLBWR). However it won't do this if only EHINV, XI, or RI bits have been set, even if that results in a reduction of permissions, so add the necessary checks to invoke the flush when these bits are set. Backports commit eff6ff9431aa9776062a5f4a08d1f6503ca9995a from qemu		2018-03-03 23:39:18 -05:00
..
cpu-qom.h
cpu.c
cpu.h	target-mips: Provide function to test if a CPU supports an ISA	2018-03-02 08:20:19 -05:00
dsp_helper.c
helper.c	mips: set CP0 Debug DExcCode for SDBBP instruction	2018-03-03 22:45:08 -05:00
helper.h
lmi_helper.c
Makefile.objs
mips-defs.h
msa_helper.c
op_helper.c	target/mips: Fix TLBWI shadow flush for EHINV,XI,RI	2018-03-03 23:39:18 -05:00
TODO
translate.c	target/mips: Fix MIPS64 MFC0 UserLocal on BE host	2018-03-03 23:37:41 -05:00
translate_init.c
unicorn.c
unicorn.h