mirror of
https://github.com/yuzu-emu/unicorn
synced 2024-11-25 05:08:51 +00:00
47150b6df3
* reg_read and reg_write now work with registers W0 through W30 in Aarch64 emulaton * Added a regress test for the ARM64 reg_read and reg_write on 32-bit registers (W0-W30) Added a new macro in uc_priv.h (WRITE_DWORD_TO_QWORD), in order to write to the lower 32 bits of a 64 bit value without overwriting the whole value when using reg_write * Fixed WRITE_DWORD macro reg_write would zero out the high order bits when writing to 32 bit registers e.g. uc.reg_write(UC_X86_REG_EAX, 0) would also set register RAX to zero
129 lines
4 KiB
C
129 lines
4 KiB
C
/* Unicorn Emulator Engine */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2015 */
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#include "hw/boards.h"
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#include "hw/arm/arm.h"
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#include "sysemu/cpus.h"
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#include "unicorn.h"
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#include "cpu.h"
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#include "unicorn_common.h"
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#include "uc_priv.h"
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const int ARM64_REGS_STORAGE_SIZE = offsetof(CPUARMState, tlb_table);
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static void arm64_set_pc(struct uc_struct *uc, uint64_t address)
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{
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((CPUARMState *)uc->current_cpu->env_ptr)->pc = address;
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}
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void arm64_release(void* ctx);
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void arm64_release(void* ctx)
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{
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TCGContext *s = (TCGContext *) ctx;
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g_free(s->tb_ctx.tbs);
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struct uc_struct* uc = s->uc;
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ARMCPU* cpu = (ARMCPU*) uc->cpu;
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g_free(cpu->cpreg_indexes);
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g_free(cpu->cpreg_values);
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g_free(cpu->cpreg_vmstate_indexes);
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g_free(cpu->cpreg_vmstate_values);
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release_common(ctx);
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}
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void arm64_reg_reset(struct uc_struct *uc)
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{
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CPUArchState *env = uc->cpu->env_ptr;
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memset(env->xregs, 0, sizeof(env->xregs));
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env->pc = 0;
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}
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int arm64_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals, int count)
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{
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CPUState *mycpu = uc->cpu;
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int i;
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for (i = 0; i < count; i++) {
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unsigned int regid = regs[i];
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void *value = vals[i];
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if (regid >= UC_ARM64_REG_X0 && regid <= UC_ARM64_REG_X28) {
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*(int64_t *)value = ARM_CPU(uc, mycpu)->env.xregs[regid - UC_ARM64_REG_X0];
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} else if (regid >= UC_ARM64_REG_W0 && regid <= UC_ARM64_REG_W30) {
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*(int32_t *)value = READ_DWORD(ARM_CPU(uc, mycpu)->env.xregs[regid - UC_ARM64_REG_W0]);
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} else {
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switch(regid) {
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default: break;
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case UC_ARM64_REG_X29:
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*(int64_t *)value = ARM_CPU(uc, mycpu)->env.xregs[29];
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break;
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case UC_ARM64_REG_X30:
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*(int64_t *)value = ARM_CPU(uc, mycpu)->env.xregs[30];
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break;
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case UC_ARM64_REG_PC:
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*(uint64_t *)value = ARM_CPU(uc, mycpu)->env.pc;
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break;
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case UC_ARM64_REG_SP:
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*(int64_t *)value = ARM_CPU(uc, mycpu)->env.xregs[31];
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break;
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}
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}
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}
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return 0;
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}
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int arm64_reg_write(struct uc_struct *uc, unsigned int *regs, void* const* vals, int count)
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{
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CPUState *mycpu = uc->cpu;
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int i;
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for (i = 0; i < count; i++) {
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unsigned int regid = regs[i];
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const void *value = vals[i];
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if (regid >= UC_ARM64_REG_X0 && regid <= UC_ARM64_REG_X28) {
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ARM_CPU(uc, mycpu)->env.xregs[regid - UC_ARM64_REG_X0] = *(uint64_t *)value;
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} else if (regid >= UC_ARM64_REG_W0 && regid <= UC_ARM64_REG_W30) {
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WRITE_DWORD(ARM_CPU(uc, mycpu)->env.xregs[regid - UC_ARM64_REG_W0], *(uint32_t *)value);
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} else {
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switch(regid) {
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default: break;
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case UC_ARM64_REG_X29:
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ARM_CPU(uc, mycpu)->env.xregs[29] = *(uint64_t *)value;
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break;
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case UC_ARM64_REG_X30:
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ARM_CPU(uc, mycpu)->env.xregs[30] = *(uint64_t *)value;
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break;
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case UC_ARM64_REG_PC:
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ARM_CPU(uc, mycpu)->env.pc = *(uint64_t *)value;
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// force to quit execution and flush TB
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uc->quit_request = true;
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uc_emu_stop(uc);
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break;
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case UC_ARM64_REG_SP:
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ARM_CPU(uc, mycpu)->env.xregs[31] = *(uint64_t *)value;
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break;
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}
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}
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}
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return 0;
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}
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__attribute__ ((visibility ("default")))
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void arm64_uc_init(struct uc_struct* uc)
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{
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register_accel_types(uc);
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arm_cpu_register_types(uc);
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aarch64_cpu_register_types(uc);
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machvirt_machine_init(uc);
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uc->reg_read = arm64_reg_read;
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uc->reg_write = arm64_reg_write;
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uc->reg_reset = arm64_reg_reset;
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uc->set_pc = arm64_set_pc;
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uc->release = arm64_release;
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uc_common_init(uc);
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}
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