mirror of
https://github.com/yuzu-emu/unicorn
synced 2024-11-24 18:18:14 +00:00
a7f59d7771
Convert all machines to use DEFINE_MACHINE() instead of QEMUMachine automatically using a script. Backports commit e264d29de28c5b0be3d063307ce9fb613b427cc3 from qemu
145 lines
3.6 KiB
C
145 lines
3.6 KiB
C
/* Unicorn Emulator Engine */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2015 */
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "hw/boards.h"
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#include "hw/mips/mips.h"
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#include "sysemu/cpus.h"
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#include "unicorn.h"
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#include "unicorn_common.h"
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#include "uc_priv.h"
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#ifdef TARGET_MIPS64
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const int MIPS64_REGS_STORAGE_SIZE = offsetof(CPUMIPSState, tlb_table);
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#else // MIPS32
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const int MIPS_REGS_STORAGE_SIZE = offsetof(CPUMIPSState, tlb_table);
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#endif
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#ifdef TARGET_MIPS64
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typedef uint64_t mipsreg_t;
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#else
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typedef uint32_t mipsreg_t;
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#endif
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static uint64_t mips_mem_redirect(uint64_t address)
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{
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// kseg0 range masks off high address bit
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if (address >= 0x80000000 && address <= 0x9fffffff)
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return address & 0x7fffffff;
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// kseg1 range masks off top 3 address bits
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if (address >= 0xa0000000 && address <= 0xbfffffff) {
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return address & 0x1fffffff;
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}
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// no redirect
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return address;
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}
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static void mips_set_pc(struct uc_struct *uc, uint64_t address)
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{
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CPUMIPSState *state = uc->cpu->env_ptr;
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state->active_tc.PC = address;
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}
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void mips_release(void *ctx);
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void mips_release(void *ctx)
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{
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TCGContext *tcg_ctx = (TCGContext *) ctx;
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MIPSCPU *cpu = MIPS_CPU(tcg_ctx->uc, tcg_ctx->uc->cpu);
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release_common(ctx);
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g_free(cpu->env.tlb);
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g_free(cpu->env.mvp);
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g_free(tcg_ctx->tb_ctx.tbs);
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}
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void mips_reg_reset(struct uc_struct *uc)
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{
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CPUArchState *env = uc->cpu->env_ptr;
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memset(env->active_tc.gpr, 0, sizeof(env->active_tc.gpr));
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env->active_tc.PC = 0;
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}
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int mips_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals, int count)
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{
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CPUState *mycpu = uc->cpu;
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CPUMIPSState *state = &MIPS_CPU(uc, mycpu)->env;
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int i;
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for (i = 0; i < count; i++) {
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unsigned int regid = regs[i];
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void *value = vals[i];
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if (regid >= UC_MIPS_REG_0 && regid <= UC_MIPS_REG_31) {
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*(mipsreg_t *)value = state->active_tc.gpr[regid - UC_MIPS_REG_0];
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} else {
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switch(regid) {
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default: break;
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case UC_MIPS_REG_PC:
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*(mipsreg_t *)value = state->active_tc.PC;
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break;
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}
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}
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}
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return 0;
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}
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int mips_reg_write(struct uc_struct *uc, unsigned int *regs, void *const *vals, int count)
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{
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CPUState *mycpu = uc->cpu;
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CPUMIPSState *state = &MIPS_CPU(uc, mycpu)->env;
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int i;
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for (i = 0; i < count; i++) {
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unsigned int regid = regs[i];
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const void *value = vals[i];
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if (regid >= UC_MIPS_REG_0 && regid <= UC_MIPS_REG_31) {
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state->active_tc.gpr[regid - UC_MIPS_REG_0] = *(mipsreg_t *)value;
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} else {
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switch(regid) {
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default: break;
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case UC_MIPS_REG_PC:
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state->active_tc.PC = *(mipsreg_t *)value;
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// force to quit execution and flush TB
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uc->quit_request = true;
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uc_emu_stop(uc);
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break;
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}
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}
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}
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return 0;
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}
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DEFAULT_VISIBILITY
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#ifdef TARGET_MIPS64
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#ifdef TARGET_WORDS_BIGENDIAN
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void mips64_uc_init(struct uc_struct* uc)
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#else
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void mips64el_uc_init(struct uc_struct* uc)
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#endif
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#else // if TARGET_MIPS
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#ifdef TARGET_WORDS_BIGENDIAN
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void mips_uc_init(struct uc_struct* uc)
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#else
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void mipsel_uc_init(struct uc_struct* uc)
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#endif
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#endif
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{
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register_accel_types(uc);
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mips_cpu_register_types(uc);
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mips_machine_init_register_types(uc);
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uc->reg_read = mips_reg_read;
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uc->reg_write = mips_reg_write;
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uc->reg_reset = mips_reg_reset;
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uc->release = mips_release;
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uc->set_pc = mips_set_pc;
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uc->mem_redirect = mips_mem_redirect;
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uc_common_init(uc);
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}
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