Lioncash b6f752970b target/riscv: Initial introduction of the RISC-V target ... This ports over the RISC-V architecture from Qemu. This is currently a very barebones transition. No code hooking or any fancy stuff. Currently, you can feed it instructions and query the CPU state itself. This also allows choosing whether or not RISC-V 32-bit or RISC-V 64-bit is desirable through Unicorn's interface as well. Extremely basic examples of executing a single instruction have been added to the samples directory to help demonstrate how to use the basic functionality.		2019-03-08 21:46:10 -05:00
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aarch64-softmmu.mak
aarch64eb-softmmu.mak
arm-softmmu.mak
armeb-softmmu.mak
i386-softmmu.mak
m68k-softmmu.mak
mips-softmmu.mak
mips64-softmmu.mak
mips64el-softmmu.mak
mipsel-softmmu.mak
ppc-softmmu.mak
ppc64-softmmu.mak
ppcemb-softmmu.mak
riscv32-softmmu.mak
riscv64-softmmu.mak
sparc-softmmu.mak
sparc64-softmmu.mak
x86_64-softmmu.mak