Bastian Koppelmann 6190837e2f target/riscv: Remove manual decoding from gen_store() ... With decodetree we don't need to convert RISC-V opcodes into to MemOps as the old gen_store() did. Backports commit bce8a342a1f0919479d18ec812b100136daa746b from qemu		2019-03-19 05:05:14 -04:00
..
accel	cputlb: update TLB entry/index after tlb_fill	2019-02-12 11:48:48 -05:00
crypto
default-configs	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00
docs
fpu	qemu/fpu: Synchronize with Qemu	2019-03-09 18:27:31 -05:00
hw	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00
include	qemu/fpu: Synchronize with Qemu	2019-03-09 18:27:31 -05:00
qapi
qobject
qom
scripts	decodetree: Properly diagnose fields overflowing an insn	2019-03-13 11:21:04 -04:00
target	target/riscv: Remove manual decoding from gen_store()	2019-03-19 05:05:14 -04:00
tcg	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00
util	mmap-alloc: fix hugetlbfs misaligned length in ppc64	2019-02-05 16:52:39 -05:00
aarch64.h	qemu/fpu: Synchronize with Qemu	2019-03-09 18:27:31 -05:00
aarch64eb.h	qemu/fpu: Synchronize with Qemu	2019-03-09 18:27:31 -05:00
accel.c
arm.h	qemu/fpu: Synchronize with Qemu	2019-03-09 18:27:31 -05:00
armeb.h	qemu/fpu: Synchronize with Qemu	2019-03-09 18:27:31 -05:00
CODING_STYLE
configure	configure: Disable W^X on OpenBSD	2019-03-11 16:46:52 -04:00
COPYING
COPYING.LIB
cpus.c
exec.c	exec.c: refactor function flatview_add_to_dispatch()	2019-03-11 17:00:46 -04:00
gen_all_header.sh
glib_compat.c	target/arm: expose remaining CPUID registers as RAZ	2019-02-15 17:48:37 -05:00
HACKING
header_gen.py	target/riscv: Convert quadrant 0 of RVXC insns to decodetree	2019-03-19 04:45:53 -04:00
ioport.c
LICENSE
m68k.h	qemu/fpu: Synchronize with Qemu	2019-03-09 18:27:31 -05:00
Makefile
Makefile.objs
Makefile.target
memory.c
memory_ldst.inc.c
memory_mapping.c
mips.h	qemu/fpu: Synchronize with Qemu	2019-03-09 18:27:31 -05:00
mips64.h	qemu/fpu: Synchronize with Qemu	2019-03-09 18:27:31 -05:00
mips64el.h	qemu/fpu: Synchronize with Qemu	2019-03-09 18:27:31 -05:00
mipsel.h	qemu/fpu: Synchronize with Qemu	2019-03-09 18:27:31 -05:00
powerpc.h	qemu/fpu: Synchronize with Qemu	2019-03-09 18:27:31 -05:00
qemu-timer.c
riscv32.h	target/riscv: Convert quadrant 0 of RVXC insns to decodetree	2019-03-19 04:45:53 -04:00
riscv64.h	target/riscv: Convert quadrant 0 of RVXC insns to decodetree	2019-03-19 04:45:53 -04:00
rules.mak
sparc.h	qemu/fpu: Synchronize with Qemu	2019-03-09 18:27:31 -05:00
sparc64.h	qemu/fpu: Synchronize with Qemu	2019-03-09 18:27:31 -05:00
unicorn_common.h
VERSION
vl.c
vl.h
x86_64.h	qemu/fpu: Synchronize with Qemu	2019-03-09 18:27:31 -05:00