Lioncash b6f752970b target/riscv: Initial introduction of the RISC-V target ... This ports over the RISC-V architecture from Qemu. This is currently a very barebones transition. No code hooking or any fancy stuff. Currently, you can feed it instructions and query the CPU state itself. This also allows choosing whether or not RISC-V 32-bit or RISC-V 64-bit is desirable through Unicorn's interface as well. Extremely basic examples of executing a single instruction have been added to the samples directory to help demonstrate how to use the basic functionality.		2019-03-08 21:46:10 -05:00
..
unicorn	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00
list.h
qemu.h	include: Move RAMList to ramlist.h	2018-02-20 08:47:51 -05:00
uc_priv.h	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00