mirror of
https://github.com/yuzu-emu/unicorn
synced 2024-11-25 07:49:02 +00:00
126 lines
3.4 KiB
C
126 lines
3.4 KiB
C
/* Unicorn Emulator Engine */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2015 */
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#include "hw/boards.h"
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#include "hw/arm/arm.h"
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#include "sysemu/cpus.h"
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#include "unicorn.h"
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#include "cpu.h"
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#include "unicorn_common.h"
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#define READ_QWORD(x) ((uint64)x)
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#define READ_DWORD(x) (x & 0xffffffff)
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#define READ_WORD(x) (x & 0xffff)
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#define READ_BYTE_H(x) ((x & 0xffff) >> 8)
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#define READ_BYTE_L(x) (x & 0xff)
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static void arm_set_pc(struct uc_struct *uc, uint64_t address)
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{
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((CPUARMState *)uc->current_cpu->env_ptr)->pc = address;
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((CPUARMState *)uc->current_cpu->env_ptr)->regs[15] = address;
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}
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void arm_reg_reset(struct uc_struct *uc)
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{
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(void)uc;
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CPUArchState *env;
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env = first_cpu->env_ptr;
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memset(env->regs, 0, sizeof(env->regs));
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env->pc = 0;
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}
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int arm_reg_read(struct uc_struct *uc, unsigned int regid, void *value)
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{
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CPUState *mycpu;
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mycpu = first_cpu;
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if (uc->mode & ~UC_MODE_ARM_MASK) {
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if (regid >= UC_ARM_REG_R0 && regid <= UC_ARM_REG_R12)
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*(int32_t *)value = ARM_CPU(uc, mycpu)->env.regs[regid - UC_ARM_REG_R0];
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else {
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switch(regid) {
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case UC_ARM_REG_CPSR:
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*(int32_t *)value = cpsr_read(&ARM_CPU(uc, mycpu)->env);
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break;
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//case UC_ARM_REG_SP:
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case UC_ARM_REG_R13:
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*(int32_t *)value = ARM_CPU(uc, mycpu)->env.regs[13];
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break;
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//case UC_ARM_REG_LR:
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case UC_ARM_REG_R14:
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*(int32_t *)value = ARM_CPU(uc, mycpu)->env.regs[14];
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break;
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//case UC_ARM_REG_PC:
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case UC_ARM_REG_R15:
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*(int32_t *)value = ARM_CPU(uc, mycpu)->env.regs[15];
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break;
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}
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}
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}
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return 0;
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}
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#define WRITE_DWORD(x, w) (x = (x & ~0xffffffff) | (w & 0xffffffff))
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#define WRITE_WORD(x, w) (x = (x & ~0xffff) | (w & 0xffff))
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#define WRITE_BYTE_H(x, b) (x = (x & ~0xff00) | (b & 0xff))
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#define WRITE_BYTE_L(x, b) (x = (x & ~0xff) | (b & 0xff))
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int arm_reg_write(struct uc_struct *uc, unsigned int regid, const void *value)
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{
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CPUState *mycpu = first_cpu;
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if (uc->mode & ~UC_MODE_ARM_MASK) {
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if (regid >= UC_ARM_REG_R0 && regid <= UC_ARM_REG_R12)
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ARM_CPU(uc, mycpu)->env.regs[regid - UC_ARM_REG_R0] = *(uint32_t *)value;
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else {
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switch(regid) {
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//case UC_ARM_REG_SP:
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case UC_ARM_REG_R13:
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ARM_CPU(uc, mycpu)->env.regs[13] = *(uint32_t *)value;
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break;
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//case UC_ARM_REG_LR:
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case UC_ARM_REG_R14:
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ARM_CPU(uc, mycpu)->env.regs[14] = *(uint32_t *)value;
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break;
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//case UC_ARM_REG_PC:
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case UC_ARM_REG_R15:
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ARM_CPU(uc, mycpu)->env.regs[15] = *(uint32_t *)value;
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break;
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}
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}
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}
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return 0;
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}
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static bool arm_stop_interrupt(int intno)
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{
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switch(intno) {
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default:
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return false;
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case EXCP_UDEF:
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return true;
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}
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}
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void arm_uc_init(struct uc_struct* uc)
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{
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register_accel_types(uc);
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arm_cpu_register_types(uc);
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tosa_machine_init(uc);
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uc->reg_read = arm_reg_read;
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uc->reg_write = arm_reg_write;
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uc->reg_reset = arm_reg_reset;
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uc->set_pc = arm_set_pc;
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uc->stop_interrupt = arm_stop_interrupt;
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uc_common_init(uc);
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}
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