mirror of
https://github.com/yuzu-emu/unicorn
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7c874b1b2b
The syscall and sysret instructions behave a bit differently: TF is checked after the instruction completes. This allows the o/s to disable #DB at a syscall by adding TF to FMASK. And then when the sysret is executed the #DB is taken "as if" the syscall insn just completed. Backports commit c52ab08aee6f7d4717fc6b517174043126bd302f from qemu
334 lines
9.3 KiB
C
334 lines
9.3 KiB
C
/*
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* i386 breakpoint helpers
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "exec/exec-all.h"
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#include "exec/helper-proto.h"
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#ifndef CONFIG_USER_ONLY
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static inline bool hw_local_breakpoint_enabled(unsigned long dr7, int index)
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{
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return (dr7 >> (index * 2)) & 1;
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}
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static inline bool hw_global_breakpoint_enabled(unsigned long dr7, int index)
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{
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return (dr7 >> (index * 2)) & 2;
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}
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static inline bool hw_breakpoint_enabled(unsigned long dr7, int index)
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{
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return hw_global_breakpoint_enabled(dr7, index) ||
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hw_local_breakpoint_enabled(dr7, index);
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}
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static inline int hw_breakpoint_type(unsigned long dr7, int index)
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{
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return (dr7 >> (DR7_TYPE_SHIFT + (index * 4))) & 3;
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}
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static inline int hw_breakpoint_len(unsigned long dr7, int index)
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{
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int len = ((dr7 >> (DR7_LEN_SHIFT + (index * 4))) & 3);
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return (len == 2) ? 8 : len + 1;
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}
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static int hw_breakpoint_insert(CPUX86State *env, int index)
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{
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CPUState *cs = CPU(x86_env_get_cpu(env));
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target_ulong dr7 = env->dr[7];
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target_ulong drN = env->dr[index];
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int err = 0;
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switch (hw_breakpoint_type(dr7, index)) {
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case DR7_TYPE_BP_INST:
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if (hw_breakpoint_enabled(dr7, index)) {
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err = cpu_breakpoint_insert(cs, drN, BP_CPU,
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&env->cpu_breakpoint[index]);
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}
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break;
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case DR7_TYPE_IO_RW:
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/* Notice when we should enable calls to bpt_io. */
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return hw_breakpoint_enabled(env->dr[7], index)
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? HF_IOBPT_MASK : 0;
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case DR7_TYPE_DATA_WR:
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if (hw_breakpoint_enabled(dr7, index)) {
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err = cpu_watchpoint_insert(cs, drN,
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hw_breakpoint_len(dr7, index),
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BP_CPU | BP_MEM_WRITE,
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&env->cpu_watchpoint[index]);
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}
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break;
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case DR7_TYPE_DATA_RW:
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if (hw_breakpoint_enabled(dr7, index)) {
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err = cpu_watchpoint_insert(cs, drN,
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hw_breakpoint_len(dr7, index),
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BP_CPU | BP_MEM_ACCESS,
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&env->cpu_watchpoint[index]);
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}
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break;
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}
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if (err) {
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env->cpu_breakpoint[index] = NULL;
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}
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return 0;
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}
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static void hw_breakpoint_remove(CPUX86State *env, int index)
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{
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CPUState *cs = CPU(x86_env_get_cpu(env));
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switch (hw_breakpoint_type(env->dr[7], index)) {
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case DR7_TYPE_BP_INST:
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if (env->cpu_breakpoint[index]) {
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cpu_breakpoint_remove_by_ref(cs, env->cpu_breakpoint[index]);
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env->cpu_breakpoint[index] = NULL;
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}
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break;
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case DR7_TYPE_DATA_WR:
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case DR7_TYPE_DATA_RW:
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if (env->cpu_breakpoint[index]) {
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cpu_watchpoint_remove_by_ref(cs, env->cpu_watchpoint[index]);
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env->cpu_breakpoint[index] = NULL;
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}
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break;
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case DR7_TYPE_IO_RW:
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/* HF_IOBPT_MASK cleared elsewhere. */
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break;
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}
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}
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void cpu_x86_update_dr7(CPUX86State *env, uint32_t new_dr7)
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{
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target_ulong old_dr7 = env->dr[7];
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int iobpt = 0;
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int i;
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new_dr7 |= DR7_FIXED_1;
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/* If nothing is changing except the global/local enable bits,
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then we can make the change more efficient. */
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if (((old_dr7 ^ new_dr7) & ~0xff) == 0) {
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/* Fold the global and local enable bits together into the
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global fields, then xor to show which registers have
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changed collective enable state. */
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int mod = ((old_dr7 | old_dr7 * 2) ^ (new_dr7 | new_dr7 * 2)) & 0xff;
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for (i = 0; i < DR7_MAX_BP; i++) {
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if ((mod & (2 << i * 2)) && !hw_breakpoint_enabled(new_dr7, i)) {
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iobpt |= hw_breakpoint_insert(env, i);
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} else if (hw_breakpoint_type(new_dr7, i) == DR7_TYPE_IO_RW
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&& hw_breakpoint_enabled(new_dr7, i)) {
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iobpt |= HF_IOBPT_MASK;
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}
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}
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env->dr[7] = new_dr7;
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for (i = 0; i < DR7_MAX_BP; i++) {
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if (mod & (2 << i * 2) && hw_breakpoint_enabled(new_dr7, i)) {
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hw_breakpoint_insert(env, i);
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}
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}
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} else {
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for (i = 0; i < DR7_MAX_BP; i++) {
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hw_breakpoint_remove(env, i);
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}
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env->dr[7] = new_dr7;
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for (i = 0; i < DR7_MAX_BP; i++) {
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iobpt |= hw_breakpoint_insert(env, i);
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}
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}
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env->hflags = (env->hflags & ~HF_IOBPT_MASK) | iobpt;
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}
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static bool check_hw_breakpoints(CPUX86State *env, bool force_dr6_update)
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{
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target_ulong dr6;
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int reg;
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bool hit_enabled = false;
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dr6 = env->dr[6] & ~0xf;
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for (reg = 0; reg < DR7_MAX_BP; reg++) {
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bool bp_match = false;
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bool wp_match = false;
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switch (hw_breakpoint_type(env->dr[7], reg)) {
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case DR7_TYPE_BP_INST:
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if (env->dr[reg] == env->eip) {
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bp_match = true;
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}
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break;
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case DR7_TYPE_DATA_WR:
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case DR7_TYPE_DATA_RW:
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if (env->cpu_watchpoint[reg] &&
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env->cpu_watchpoint[reg]->flags & BP_WATCHPOINT_HIT) {
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wp_match = true;
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}
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break;
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case DR7_TYPE_IO_RW:
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break;
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}
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if (bp_match || wp_match) {
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dr6 |= 1ULL << reg;
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if (hw_breakpoint_enabled(env->dr[7], reg)) {
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hit_enabled = true;
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}
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}
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}
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if (hit_enabled || force_dr6_update) {
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env->dr[6] = dr6;
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}
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return hit_enabled;
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}
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void breakpoint_handler(CPUState *cs)
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{
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X86CPU *cpu = X86_CPU(cs->uc, cs);
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CPUX86State *env = &cpu->env;
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CPUBreakpoint *bp;
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if (cs->watchpoint_hit) {
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if (cs->watchpoint_hit->flags & BP_CPU) {
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cs->watchpoint_hit = NULL;
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if (check_hw_breakpoints(env, false)) {
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raise_exception(env, EXCP01_DB);
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} else {
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cpu_loop_exit_noexc(cs);
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}
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}
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} else {
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QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
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if (bp->pc == env->eip) {
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if (bp->flags & BP_CPU) {
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check_hw_breakpoints(env, true);
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raise_exception(env, EXCP01_DB);
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}
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break;
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}
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}
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}
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}
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#endif
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void helper_single_step(CPUX86State *env)
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{
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#ifndef CONFIG_USER_ONLY
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check_hw_breakpoints(env, true);
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env->dr[6] |= DR6_BS;
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#endif
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raise_exception(env, EXCP01_DB);
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}
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void helper_rechecking_single_step(CPUX86State *env)
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{
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if ((env->eflags & TF_MASK) != 0) {
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helper_single_step(env);
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}
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}
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void helper_set_dr(CPUX86State *env, int reg, target_ulong t0)
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{
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#ifndef CONFIG_USER_ONLY
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switch (reg) {
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case 0: case 1: case 2: case 3:
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if (hw_breakpoint_enabled(env->dr[7], reg)
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&& hw_breakpoint_type(env->dr[7], reg) != DR7_TYPE_IO_RW) {
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hw_breakpoint_remove(env, reg);
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env->dr[reg] = t0;
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hw_breakpoint_insert(env, reg);
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} else {
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env->dr[reg] = t0;
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}
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return;
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case 4:
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if (env->cr[4] & CR4_DE_MASK) {
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break;
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}
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/* fallthru */
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case 6:
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env->dr[6] = t0;
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return;
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case 5:
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if (env->cr[4] & CR4_DE_MASK) {
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break;
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}
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/* fallthru */
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case 7:
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cpu_x86_update_dr7(env, t0);
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return;
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}
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raise_exception_err_ra(env, EXCP06_ILLOP, 0, GETPC());
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#endif
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}
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target_ulong helper_get_dr(CPUX86State *env, int reg)
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{
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switch (reg) {
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case 0: case 1: case 2: case 3: case 6: case 7:
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return env->dr[reg];
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case 4:
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if (env->cr[4] & CR4_DE_MASK) {
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break;
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} else {
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return env->dr[6];
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}
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case 5:
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if (env->cr[4] & CR4_DE_MASK) {
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break;
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} else {
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return env->dr[7];
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}
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}
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raise_exception_err_ra(env, EXCP06_ILLOP, 0, GETPC());
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}
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/* Check if Port I/O is trapped by a breakpoint. */
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void helper_bpt_io(CPUX86State *env, uint32_t port,
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uint32_t size, target_ulong next_eip)
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{
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#ifndef CONFIG_USER_ONLY
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target_ulong dr7 = env->dr[7];
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int i, hit = 0;
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for (i = 0; i < DR7_MAX_BP; ++i) {
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if (hw_breakpoint_type(dr7, i) == DR7_TYPE_IO_RW
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&& hw_breakpoint_enabled(dr7, i)) {
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int bpt_len = hw_breakpoint_len(dr7, i);
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if (port + size - 1 >= env->dr[i]
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&& port <= env->dr[i] + bpt_len - 1) {
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hit |= 1 << i;
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}
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}
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}
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if (hit) {
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env->dr[6] = (env->dr[6] & ~0xf) | hit;
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env->eip = next_eip;
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raise_exception(env, EXCP01_DB);
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}
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#endif
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}
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