mirror of
https://github.com/yuzu-emu/unicorn
synced 2024-11-25 11:19:01 +00:00
b2f1326437
We've currently got 18 architectures in QEMU, and thus 18 target-xxx folders in the root folder of the QEMU source tree. More architectures (e.g. RISC-V, AVR) are likely to be included soon, too, so the main folder of the QEMU sources slowly gets quite overcrowded with the target-xxx folders. To disburden the main folder a little bit, let's move the target-xxx folders into a dedicated target/ folder, so that target-xxx/ simply becomes target/xxx/ instead. Backports commit fcf5ef2ab52c621a4617ebbef36bf43b4003f4c0 from qemu
90 lines
2.7 KiB
C
90 lines
2.7 KiB
C
/*
|
|
* QEMU ARM CPU
|
|
*
|
|
* Copyright (c) 2012 SUSE LINUX Products GmbH
|
|
*
|
|
* This program is free software; you can redistribute it and/or
|
|
* modify it under the terms of the GNU General Public License
|
|
* as published by the Free Software Foundation; either version 2
|
|
* of the License, or (at your option) any later version.
|
|
*
|
|
* This program is distributed in the hope that it will be useful,
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
* GNU General Public License for more details.
|
|
*
|
|
* You should have received a copy of the GNU General Public License
|
|
* along with this program; if not, see
|
|
* <http://www.gnu.org/licenses/gpl-2.0.html>
|
|
*/
|
|
#ifndef QEMU_ARM_CPU_QOM_H
|
|
#define QEMU_ARM_CPU_QOM_H
|
|
|
|
#include "qom/cpu.h"
|
|
|
|
#define TYPE_ARM_CPU "arm-cpu"
|
|
|
|
#define ARM_CPU_CLASS(uc, klass) \
|
|
OBJECT_CLASS_CHECK(uc, ARMCPUClass, (klass), TYPE_ARM_CPU)
|
|
#define ARM_CPU(uc, obj) ((ARMCPU *)obj)
|
|
#define ARM_CPU_GET_CLASS(uc, obj) \
|
|
OBJECT_GET_CLASS(uc, ARMCPUClass, (obj), TYPE_ARM_CPU)
|
|
|
|
/**
|
|
* ARMCPUClass:
|
|
* @parent_realize: The parent class' realize handler.
|
|
* @parent_reset: The parent class' reset handler.
|
|
*
|
|
* An ARM CPU model.
|
|
*/
|
|
typedef struct ARMCPUClass {
|
|
/*< private >*/
|
|
CPUClass parent_class;
|
|
/*< public >*/
|
|
|
|
DeviceRealize parent_realize;
|
|
void (*parent_reset)(CPUState *cpu);
|
|
} ARMCPUClass;
|
|
|
|
typedef struct ARMCPU ARMCPU;
|
|
|
|
#define TYPE_AARCH64_CPU "aarch64-cpu"
|
|
#define AARCH64_CPU_CLASS(klass) \
|
|
OBJECT_CLASS_CHECK(AArch64CPUClass, (klass), TYPE_AARCH64_CPU)
|
|
#define AARCH64_CPU_GET_CLASS(obj) \
|
|
OBJECT_GET_CLASS(AArch64CPUClass, (obj), TYPE_AArch64_CPU)
|
|
|
|
typedef struct AArch64CPUClass {
|
|
/*< private >*/
|
|
ARMCPUClass parent_class;
|
|
/*< public >*/
|
|
} AArch64CPUClass;
|
|
|
|
void register_cp_regs_for_features(ARMCPU *cpu);
|
|
void init_cpreg_list(ARMCPU *cpu);
|
|
|
|
/* Callback functions for the generic timer's timers. */
|
|
void arm_gt_ptimer_cb(void *opaque);
|
|
void arm_gt_vtimer_cb(void *opaque);
|
|
void arm_gt_htimer_cb(void *opaque);
|
|
void arm_gt_stimer_cb(void *opaque);
|
|
|
|
#define ARM_AFF0_SHIFT 0
|
|
#define ARM_AFF0_MASK (0xFFULL << ARM_AFF0_SHIFT)
|
|
#define ARM_AFF1_SHIFT 8
|
|
#define ARM_AFF1_MASK (0xFFULL << ARM_AFF1_SHIFT)
|
|
#define ARM_AFF2_SHIFT 16
|
|
#define ARM_AFF2_MASK (0xFFULL << ARM_AFF2_SHIFT)
|
|
#define ARM_AFF3_SHIFT 32
|
|
#define ARM_AFF3_MASK (0xFFULL << ARM_AFF3_SHIFT)
|
|
|
|
#define ARM32_AFFINITY_MASK (ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK)
|
|
#define ARM64_AFFINITY_MASK \
|
|
(ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK|ARM_AFF3_MASK)
|
|
|
|
#ifdef TARGET_AARCH64
|
|
int aarch64_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
|
|
int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
|
|
#endif
|
|
|
|
#endif
|