Peter Maydell 22dadac875 target-arm: Implement FPEXC32_EL2 system register ... The AArch64 FPEXC32_EL2 system register is visible at EL2 and EL3, and allows those exception levels to read and write the FPEXC register for a lower exception level that is using AArch32. Backports commit 03fbf20f4da58f41998dc10ec7542f65d37ba759 from qemu		2018-02-18 22:52:54 -05:00
..
arm_ldst.h
cpu-qom.h	target-arm: Use a single entry point for AArch64 and AArch32 exceptions	2018-02-18 22:34:31 -05:00
cpu.c	target-arm: Implement cpu_get_phys_page_attrs_debug	2018-02-18 22:15:50 -05:00
cpu.h	target-arm: Properly support EL2 and EL3 in arm_el_is_aa64()	2018-02-18 22:20:51 -05:00
cpu64.c	target-arm: Use a single entry point for AArch64 and AArch32 exceptions	2018-02-18 22:34:31 -05:00
crypto_helper.c	target-arm: Clean up includes	2018-02-17 21:09:32 -05:00
helper-a64.c	target-arm: Move aarch64_cpu_do_interrupt() to helper.c	2018-02-18 22:23:06 -05:00
helper-a64.h
helper.c	target-arm: Implement FPEXC32_EL2 system register	2018-02-18 22:52:54 -05:00
helper.h	target-arm: Fix CPU breakpoint handling	2018-02-17 15:24:02 -05:00
internals.h	target-arm: Use the right MMU index in arm_regime_using_lpae_format	2018-02-17 20:56:32 -05:00
iwmmxt_helper.c	target-arm: Clean up includes	2018-02-17 21:09:32 -05:00
kvm-consts.h
Makefile.objs
neon_helper.c	target-arm: Clean up includes	2018-02-17 21:09:32 -05:00
op_addsub.h
op_helper.c	target-arm: ignore ELR_ELx[1] for exception return to 32-bit ARM mode	2018-02-18 22:50:18 -05:00
psci.c
translate-a64.c	target-arm: Clean up includes	2018-02-17 21:09:32 -05:00
translate.c	target-arm: Clean up includes	2018-02-17 21:09:32 -05:00
translate.h	tcg: Remove gen_intermediate_code_pc	2018-02-17 15:23:59 -05:00
unicorn.h
unicorn_aarch64.c	target-arm: rename c1_coproc to cpacr_el1	2018-02-12 20:46:00 -05:00
unicorn_arm.c	target-arm: Add registers for PMSAv7	2018-02-17 15:22:43 -05:00