James Hogan 7e9b84ca1a target/mips: Add an MMU mode for ERL ... The segmentation control feature allows a legacy memory segment to become unmapped uncached at error level (according to CP0_Status.ERL), and in fact the user segment is already treated in this way by QEMU. Add a new MMU mode for this state so that QEMU's mappings don't persist between ERL=0 and ERL=1. Backports commit 42c86612d507c2a8789f2b8d920a244693c4ef7b from qemu		2018-03-04 00:47:19 -05:00
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cpu-qom.h
cpu.c
cpu.h	target/mips: Add an MMU mode for ERL	2018-03-04 00:47:19 -05:00
dsp_helper.c
helper.c	target/mips: Check memory permissions with mem_idx	2018-03-04 00:40:22 -05:00
helper.h	target-mips: make ITC Configuration Tags accessible to the CPU	2018-03-04 00:34:30 -05:00
lmi_helper.c
Makefile.objs
mips-defs.h
msa_helper.c
op_helper.c	target/mips: Add an MMU mode for ERL	2018-03-04 00:47:19 -05:00
TODO
translate.c	target/mips: Abstract mmu_idx from hflags	2018-03-04 00:45:00 -05:00
translate_init.c	target-mips: enable CM GCR in MIPS64R6-generic CPU	2018-03-04 00:24:09 -05:00
unicorn.c
unicorn.h