Peter Crosthwaite 91cf36e372 target-arm: cpu64: generalise name of A57 regs ... Rename some A57 CP register variables in preparation for support for Cortex A53. Use "a57_a53" to describe the shareable features. Some of the CP15 registers (such as ACTLR) are specific to implementation, but we currently just RAZ them so continue with that as the policy for both A57 and A53 processors under a shared definition. Backports commit ee804264ddc4d3cd36a5183a09847e391da0fc66 from qemu		2018-02-12 21:23:48 -05:00
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arm_ldst.h
cpu-qom.h
cpu.c	target-arm: Adjust id_aa64pfr0 when has_el3 CPU property disabled	2018-02-12 20:47:32 -05:00
cpu.h	tcg: Delete unused cpu_pc_from_tb()	2018-02-12 21:14:22 -05:00
cpu64.c	target-arm: cpu64: generalise name of A57 regs	2018-02-12 21:23:48 -05:00
crypto_helper.c
helper-a64.c	target-arm: Store SPSR_EL1 state in banked_spsr[1] (SPSR_svc)	2018-02-12 16:36:44 -05:00
helper-a64.h
helper.c	Allow ARMv8 SCR.SMD updates	2018-02-12 20:48:34 -05:00
helper.h
internals.h	target-arm: Store SPSR_EL1 state in banked_spsr[1] (SPSR_svc)	2018-02-12 16:36:44 -05:00
iwmmxt_helper.c
kvm-consts.h
Makefile.objs
neon_helper.c
op_addsub.h
op_helper.c	target-arm: Add 32/64-bit register sync	2018-02-12 14:57:20 -05:00
psci.c
translate-a64.c	target-arm: A64: Avoid signed shifts in disas_ldst_pair()	2018-02-12 15:05:09 -05:00
translate.c	target-arm: Avoid buffer overrun on UNPREDICTABLE ldrd/strd	2018-02-12 17:17:23 -05:00
translate.h	target-arm: Define correct mmu_idx values and pass them in TB flags	2018-02-12 11:21:19 -05:00
unicorn.h
unicorn_aarch64.c	target-arm: rename c1_coproc to cpacr_el1	2018-02-12 20:46:00 -05:00
unicorn_arm.c