mirror of
https://github.com/yuzu-emu/unicorn
synced 2024-11-25 17:45:29 +00:00
5b02b2728a
Right now, the AVX512 registers are split in many different fields: xmm_regs for the low 128 bits of the first 16 registers, ymmh_regs for the next 128 bits of the same first 16 registers, zmmh_regs for the next 256 bits of the same first 16 registers, and finally hi16_zmm_regs for the full 512 bits of the second 16 bit registers. This makes it simple to move data in and out of the xsave region, but would be a nightmare for a hypothetical TCG implementation and leads to a proliferation of [XYZ]MM_[BWLSQD] macros. Instead, this patch marshals data manually from the xsave region to a single 32x512-bit array, simplifying the macro jungle and clarifying which bits are in which vmstate subsection. The migration format is unaffected. Backports commit b7711471f551aa4419f9d46a11121f48ced422da from qemu
1363 lines
62 KiB
C
1363 lines
62 KiB
C
/* Unicorn Emulator Engine */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2015 */
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#include "hw/boards.h"
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#include "hw/i386/pc.h"
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#include "sysemu/cpus.h"
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#include "unicorn.h"
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#include "cpu.h"
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#include "tcg.h"
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#include "unicorn_common.h"
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#include <unicorn/x86.h> /* needed for uc_x86_mmr */
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#include "uc_priv.h"
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#define X86_NON_CS_FLAGS (DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | DESC_A_MASK)
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static void load_seg_16_helper(CPUX86State *env, int seg, uint32_t selector)
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{
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cpu_x86_load_seg_cache(env, seg, selector, (selector << 4), 0xffff, X86_NON_CS_FLAGS);
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}
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extern void helper_wrmsr(CPUX86State *env);
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extern void helper_rdmsr(CPUX86State *env);
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const int X86_REGS_STORAGE_SIZE = offsetof(CPUX86State, tlb_table);
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static void x86_set_pc(struct uc_struct *uc, uint64_t address)
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{
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((CPUX86State *)uc->current_cpu->env_ptr)->eip = address;
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}
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void x86_release(void *ctx);
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void x86_release(void *ctx)
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{
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int i;
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TCGContext *s = (TCGContext *) ctx;
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release_common(ctx);
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// arch specific
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g_free(s->cpu_A0);
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g_free(s->cpu_T[0]);
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g_free(s->cpu_T[1]);
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g_free(s->cpu_tmp0);
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g_free(s->cpu_tmp4);
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g_free(s->cpu_cc_srcT);
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g_free(s->cpu_cc_dst);
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g_free(s->cpu_cc_src);
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g_free(s->cpu_cc_src2);
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for (i = 0; i < CPU_NB_REGS; ++i) {
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g_free(s->cpu_regs[i]);
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}
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g_free(s->tb_ctx.tbs);
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}
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void x86_reg_reset(struct uc_struct *uc)
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{
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CPUArchState *env = uc->cpu->env_ptr;
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env->features[FEAT_1_EDX] = CPUID_CX8 | CPUID_CMOV | CPUID_SSE2 | CPUID_FXSR | CPUID_SSE | CPUID_CLFLUSH;
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env->features[FEAT_1_ECX] = CPUID_EXT_SSSE3 | CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_AES;
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env->features[FEAT_8000_0001_EDX] = CPUID_EXT2_3DNOW | CPUID_EXT2_RDTSCP;
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env->features[FEAT_8000_0001_ECX] = CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_SKINIT | CPUID_EXT3_CR8LEG;
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env->features[FEAT_7_0_EBX] = CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP;
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memset(env->regs, 0, sizeof(env->regs));
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memset(env->segs, 0, sizeof(env->segs));
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memset(env->cr, 0, sizeof(env->cr));
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memset(&env->ldt, 0, sizeof(env->ldt));
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memset(&env->gdt, 0, sizeof(env->gdt));
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memset(&env->tr, 0, sizeof(env->tr));
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memset(&env->idt, 0, sizeof(env->idt));
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env->eip = 0;
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env->eflags = 0;
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env->eflags0 = 0;
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env->cc_op = CC_OP_EFLAGS;
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env->fpstt = 0; /* top of stack index */
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env->fpus = 0;
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env->fpuc = 0;
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memset(env->fptags, 0, sizeof(env->fptags)); /* 0 = valid, 1 = empty */
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env->mxcsr = 0;
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memset(env->xmm_regs, 0, sizeof(env->xmm_regs));
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memset(&env->xmm_t0, 0, sizeof(env->xmm_t0));
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memset(&env->mmx_t0, 0, sizeof(env->mmx_t0));
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memset(env->opmask_regs, 0, sizeof(env->opmask_regs));
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/* sysenter registers */
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env->sysenter_cs = 0;
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env->sysenter_esp = 0;
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env->sysenter_eip = 0;
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env->efer = 0;
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env->star = 0;
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env->vm_hsave = 0;
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env->tsc = 0;
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env->tsc_adjust = 0;
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env->tsc_deadline = 0;
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env->mcg_status = 0;
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env->msr_ia32_misc_enable = 0;
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env->msr_ia32_feature_control = 0;
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env->msr_fixed_ctr_ctrl = 0;
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env->msr_global_ctrl = 0;
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env->msr_global_status = 0;
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env->msr_global_ovf_ctrl = 0;
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memset(env->msr_fixed_counters, 0, sizeof(env->msr_fixed_counters));
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memset(env->msr_gp_counters, 0, sizeof(env->msr_gp_counters));
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memset(env->msr_gp_evtsel, 0, sizeof(env->msr_gp_evtsel));
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#ifdef TARGET_X86_64
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env->lstar = 0;
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env->cstar = 0;
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env->fmask = 0;
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env->kernelgsbase = 0;
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#endif
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// TODO: reset other registers in CPUX86State qemu/target-i386/cpu.h
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// properly initialize internal setup for each mode
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switch(uc->mode) {
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default:
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break;
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case UC_MODE_16:
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env->hflags = 0;
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env->cr[0] = 0;
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//undo the damage done by the memset of env->segs above
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//for R_CS, not quite the same as x86_cpu_reset
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cpu_x86_load_seg_cache(env, R_CS, 0, 0, 0xffff,
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DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
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DESC_R_MASK | DESC_A_MASK);
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//remainder yields same state as x86_cpu_reset
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load_seg_16_helper(env, R_DS, 0);
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load_seg_16_helper(env, R_ES, 0);
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load_seg_16_helper(env, R_SS, 0);
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load_seg_16_helper(env, R_FS, 0);
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load_seg_16_helper(env, R_GS, 0);
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break;
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case UC_MODE_32:
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env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_OSFXSR_MASK;
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cpu_x86_update_cr0(env, CR0_PE_MASK); // protected mode
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break;
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case UC_MODE_64:
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env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK | HF_LMA_MASK | HF_OSFXSR_MASK;
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env->hflags &= ~(HF_ADDSEG_MASK);
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cpu_x86_update_cr0(env, CR0_PE_MASK); // protected mode
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break;
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}
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}
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static int x86_msr_read(struct uc_struct *uc, uc_x86_msr *msr)
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{
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CPUX86State *env = (CPUX86State *)uc->cpu->env_ptr;
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uint64_t ecx = env->regs[R_ECX];
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uint64_t eax = env->regs[R_EAX];
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uint64_t edx = env->regs[R_EDX];
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env->regs[R_ECX] = msr->rid;
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helper_rdmsr(env);
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msr->value = ((uint32_t)env->regs[R_EAX]) |
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((uint64_t)((uint32_t)env->regs[R_EDX]) << 32);
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env->regs[R_EAX] = eax;
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env->regs[R_ECX] = ecx;
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env->regs[R_EDX] = edx;
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/* The implementation doesn't throw exception or return an error if there is one, so
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* we will return 0. */
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return 0;
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}
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static int x86_msr_write(struct uc_struct *uc, uc_x86_msr *msr)
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{
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CPUX86State *env = (CPUX86State *)uc->cpu->env_ptr;
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uint64_t ecx = env->regs[R_ECX];
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uint64_t eax = env->regs[R_EAX];
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uint64_t edx = env->regs[R_EDX];
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env->regs[R_ECX] = msr->rid;
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env->regs[R_EAX] = (unsigned int)msr->value;
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env->regs[R_EDX] = (unsigned int)(msr->value >> 32);
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helper_wrmsr(env);
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env->regs[R_ECX] = ecx;
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env->regs[R_EAX] = eax;
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env->regs[R_EDX] = edx;
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/* The implementation doesn't throw exception or return an error if there is one, so
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* we will return 0. */
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return 0;
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}
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int x86_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals, int count)
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{
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CPUState *mycpu = uc->cpu;
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int i;
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for (i = 0; i < count; i++) {
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unsigned int regid = regs[i];
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void *value = vals[i];
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switch(regid) {
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default:
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break;
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case UC_X86_REG_FP0:
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case UC_X86_REG_FP1:
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case UC_X86_REG_FP2:
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case UC_X86_REG_FP3:
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case UC_X86_REG_FP4:
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case UC_X86_REG_FP5:
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case UC_X86_REG_FP6:
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case UC_X86_REG_FP7:
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{
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floatx80 reg = X86_CPU(uc, mycpu)->env.fpregs[regid - UC_X86_REG_FP0].d;
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cpu_get_fp80(value, (uint16_t*)((char*)value+sizeof(uint64_t)), reg);
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}
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continue;
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case UC_X86_REG_FPSW:
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{
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uint16_t fpus = X86_CPU(uc, mycpu)->env.fpus;
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fpus = fpus & ~0x3800;
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fpus |= ( X86_CPU(uc, mycpu)->env.fpstt & 0x7 ) << 11;
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*(uint16_t*) value = fpus;
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}
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continue;
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case UC_X86_REG_FPCW:
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*(uint16_t*) value = X86_CPU(uc, mycpu)->env.fpuc;
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continue;
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case UC_X86_REG_FPTAG:
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{
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#define EXPD(fp) (fp.l.upper & 0x7fff)
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#define MANTD(fp) (fp.l.lower)
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#define MAXEXPD 0x7fff
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int fptag, exp, i;
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uint64_t mant;
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CPU_LDoubleU tmp;
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fptag = 0;
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for (i = 7; i >= 0; i--) {
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fptag <<= 2;
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if (X86_CPU(uc, mycpu)->env.fptags[i]) {
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fptag |= 3;
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} else {
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tmp.d = X86_CPU(uc, mycpu)->env.fpregs[i].d;
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exp = EXPD(tmp);
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mant = MANTD(tmp);
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if (exp == 0 && mant == 0) {
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/* zero */
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fptag |= 1;
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} else if (exp == 0 || exp == MAXEXPD
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|| (mant & (1LL << 63)) == 0) {
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/* NaNs, infinity, denormal */
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fptag |= 2;
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}
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}
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}
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*(uint16_t*) value = fptag;
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}
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continue;
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case UC_X86_REG_XMM0:
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case UC_X86_REG_XMM1:
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case UC_X86_REG_XMM2:
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case UC_X86_REG_XMM3:
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case UC_X86_REG_XMM4:
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case UC_X86_REG_XMM5:
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case UC_X86_REG_XMM6:
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case UC_X86_REG_XMM7:
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{
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float64 *dst = (float64*)value;
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XMMReg *reg = &X86_CPU(uc, mycpu)->env.xmm_regs[regid - UC_X86_REG_XMM0];
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dst[0] = reg->XMM_D(0);
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dst[1] = reg->XMM_D(1);
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continue;
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}
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case UC_X86_REG_YMM0:
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case UC_X86_REG_YMM1:
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case UC_X86_REG_YMM2:
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case UC_X86_REG_YMM3:
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case UC_X86_REG_YMM4:
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case UC_X86_REG_YMM5:
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case UC_X86_REG_YMM6:
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case UC_X86_REG_YMM7:
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{
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float64 *dst = (float64*)value;
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XMMReg *reg = &X86_CPU(uc, mycpu)->env.xmm_regs[regid - UC_X86_REG_XMM0];
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dst[0] = reg->XMM_D(0);
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dst[1] = reg->XMM_D(1);
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dst[2] = reg->XMM_D(2);
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dst[3] = reg->XMM_D(3);
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continue;
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}
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}
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switch(uc->mode) {
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default:
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break;
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case UC_MODE_16:
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switch(regid) {
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default: break;
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case UC_X86_REG_ES:
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*(int16_t *)value = X86_CPU(uc, mycpu)->env.segs[R_ES].selector;
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continue;
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case UC_X86_REG_SS:
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*(int16_t *)value = X86_CPU(uc, mycpu)->env.segs[R_SS].selector;
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continue;
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case UC_X86_REG_DS:
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*(int16_t *)value = X86_CPU(uc, mycpu)->env.segs[R_DS].selector;
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continue;
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case UC_X86_REG_FS:
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*(int16_t *)value = X86_CPU(uc, mycpu)->env.segs[R_FS].selector;
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continue;
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case UC_X86_REG_GS:
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*(int16_t *)value = X86_CPU(uc, mycpu)->env.segs[R_GS].selector;
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continue;
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}
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// fall-thru
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case UC_MODE_32:
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switch(regid) {
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default:
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break;
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case UC_X86_REG_CR0:
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case UC_X86_REG_CR1:
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case UC_X86_REG_CR2:
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case UC_X86_REG_CR3:
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case UC_X86_REG_CR4:
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*(int32_t *)value = X86_CPU(uc, mycpu)->env.cr[regid - UC_X86_REG_CR0];
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break;
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case UC_X86_REG_DR0:
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case UC_X86_REG_DR1:
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case UC_X86_REG_DR2:
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case UC_X86_REG_DR3:
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case UC_X86_REG_DR4:
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case UC_X86_REG_DR5:
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case UC_X86_REG_DR6:
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case UC_X86_REG_DR7:
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*(int32_t *)value = X86_CPU(uc, mycpu)->env.dr[regid - UC_X86_REG_DR0];
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break;
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case UC_X86_REG_EFLAGS:
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*(int32_t *)value = cpu_compute_eflags(&X86_CPU(uc, mycpu)->env);
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break;
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case UC_X86_REG_EAX:
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*(int32_t *)value = X86_CPU(uc, mycpu)->env.regs[R_EAX];
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break;
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case UC_X86_REG_AX:
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*(int16_t *)value = READ_WORD(X86_CPU(uc, mycpu)->env.regs[R_EAX]);
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break;
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case UC_X86_REG_AH:
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*(int8_t *)value = READ_BYTE_H(X86_CPU(uc, mycpu)->env.regs[R_EAX]);
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break;
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case UC_X86_REG_AL:
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*(int8_t *)value = READ_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_EAX]);
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break;
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case UC_X86_REG_EBX:
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*(int32_t *)value = X86_CPU(uc, mycpu)->env.regs[R_EBX];
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break;
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case UC_X86_REG_BX:
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*(int16_t *)value = READ_WORD(X86_CPU(uc, mycpu)->env.regs[R_EBX]);
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break;
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case UC_X86_REG_BH:
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*(int8_t *)value = READ_BYTE_H(X86_CPU(uc, mycpu)->env.regs[R_EBX]);
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break;
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case UC_X86_REG_BL:
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*(int8_t *)value = READ_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_EBX]);
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break;
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case UC_X86_REG_ECX:
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*(int32_t *)value = X86_CPU(uc, mycpu)->env.regs[R_ECX];
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break;
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case UC_X86_REG_CX:
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*(int16_t *)value = READ_WORD(X86_CPU(uc, mycpu)->env.regs[R_ECX]);
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break;
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case UC_X86_REG_CH:
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*(int8_t *)value = READ_BYTE_H(X86_CPU(uc, mycpu)->env.regs[R_ECX]);
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break;
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case UC_X86_REG_CL:
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*(int8_t *)value = READ_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_ECX]);
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break;
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case UC_X86_REG_EDX:
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*(int32_t *)value = X86_CPU(uc, mycpu)->env.regs[R_EDX];
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break;
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case UC_X86_REG_DX:
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*(int16_t *)value = READ_WORD(X86_CPU(uc, mycpu)->env.regs[R_EDX]);
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break;
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case UC_X86_REG_DH:
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*(int8_t *)value = READ_BYTE_H(X86_CPU(uc, mycpu)->env.regs[R_EDX]);
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break;
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case UC_X86_REG_DL:
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*(int8_t *)value = READ_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_EDX]);
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break;
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case UC_X86_REG_ESP:
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*(int32_t *)value = X86_CPU(uc, mycpu)->env.regs[R_ESP];
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break;
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case UC_X86_REG_SP:
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*(int16_t *)value = READ_WORD(X86_CPU(uc, mycpu)->env.regs[R_ESP]);
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break;
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case UC_X86_REG_EBP:
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*(int32_t *)value = X86_CPU(uc, mycpu)->env.regs[R_EBP];
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break;
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case UC_X86_REG_BP:
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*(int16_t *)value = READ_WORD(X86_CPU(uc, mycpu)->env.regs[R_EBP]);
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break;
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case UC_X86_REG_ESI:
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*(int32_t *)value = X86_CPU(uc, mycpu)->env.regs[R_ESI];
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break;
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case UC_X86_REG_SI:
|
|
*(int16_t *)value = READ_WORD(X86_CPU(uc, mycpu)->env.regs[R_ESI]);
|
|
break;
|
|
case UC_X86_REG_EDI:
|
|
*(int32_t *)value = X86_CPU(uc, mycpu)->env.regs[R_EDI];
|
|
break;
|
|
case UC_X86_REG_DI:
|
|
*(int16_t *)value = READ_WORD(X86_CPU(uc, mycpu)->env.regs[R_EDI]);
|
|
break;
|
|
case UC_X86_REG_EIP:
|
|
*(int32_t *)value = X86_CPU(uc, mycpu)->env.eip;
|
|
break;
|
|
case UC_X86_REG_IP:
|
|
*(int16_t *)value = READ_WORD(X86_CPU(uc, mycpu)->env.eip);
|
|
break;
|
|
case UC_X86_REG_CS:
|
|
*(int16_t *)value = (uint16_t)X86_CPU(uc, mycpu)->env.segs[R_CS].selector;
|
|
break;
|
|
case UC_X86_REG_DS:
|
|
*(int16_t *)value = (uint16_t)X86_CPU(uc, mycpu)->env.segs[R_DS].selector;
|
|
break;
|
|
case UC_X86_REG_SS:
|
|
*(int16_t *)value = (uint16_t)X86_CPU(uc, mycpu)->env.segs[R_SS].selector;
|
|
break;
|
|
case UC_X86_REG_ES:
|
|
*(int16_t *)value = (uint16_t)X86_CPU(uc, mycpu)->env.segs[R_ES].selector;
|
|
break;
|
|
case UC_X86_REG_FS:
|
|
*(int16_t *)value = (uint16_t)X86_CPU(uc, mycpu)->env.segs[R_FS].selector;
|
|
break;
|
|
case UC_X86_REG_GS:
|
|
*(int16_t *)value = (uint16_t)X86_CPU(uc, mycpu)->env.segs[R_GS].selector;
|
|
break;
|
|
case UC_X86_REG_IDTR:
|
|
((uc_x86_mmr *)value)->limit = (uint16_t)X86_CPU(uc, mycpu)->env.idt.limit;
|
|
((uc_x86_mmr *)value)->base = (uint32_t)X86_CPU(uc, mycpu)->env.idt.base;
|
|
break;
|
|
case UC_X86_REG_GDTR:
|
|
((uc_x86_mmr *)value)->limit = (uint16_t)X86_CPU(uc, mycpu)->env.gdt.limit;
|
|
((uc_x86_mmr *)value)->base = (uint32_t)X86_CPU(uc, mycpu)->env.gdt.base;
|
|
break;
|
|
case UC_X86_REG_LDTR:
|
|
((uc_x86_mmr *)value)->limit = X86_CPU(uc, mycpu)->env.ldt.limit;
|
|
((uc_x86_mmr *)value)->base = (uint32_t)X86_CPU(uc, mycpu)->env.ldt.base;
|
|
((uc_x86_mmr *)value)->selector = (uint16_t)X86_CPU(uc, mycpu)->env.ldt.selector;
|
|
((uc_x86_mmr *)value)->flags = X86_CPU(uc, mycpu)->env.ldt.flags;
|
|
break;
|
|
case UC_X86_REG_TR:
|
|
((uc_x86_mmr *)value)->limit = X86_CPU(uc, mycpu)->env.tr.limit;
|
|
((uc_x86_mmr *)value)->base = (uint32_t)X86_CPU(uc, mycpu)->env.tr.base;
|
|
((uc_x86_mmr *)value)->selector = (uint16_t)X86_CPU(uc, mycpu)->env.tr.selector;
|
|
((uc_x86_mmr *)value)->flags = X86_CPU(uc, mycpu)->env.tr.flags;
|
|
break;
|
|
case UC_X86_REG_MSR:
|
|
x86_msr_read(uc, (uc_x86_msr *)value);
|
|
break;
|
|
}
|
|
break;
|
|
|
|
#ifdef TARGET_X86_64
|
|
case UC_MODE_64:
|
|
switch(regid) {
|
|
default:
|
|
break;
|
|
case UC_X86_REG_CR0:
|
|
case UC_X86_REG_CR1:
|
|
case UC_X86_REG_CR2:
|
|
case UC_X86_REG_CR3:
|
|
case UC_X86_REG_CR4:
|
|
*(int64_t *)value = X86_CPU(uc, mycpu)->env.cr[regid - UC_X86_REG_CR0];
|
|
break;
|
|
case UC_X86_REG_DR0:
|
|
case UC_X86_REG_DR1:
|
|
case UC_X86_REG_DR2:
|
|
case UC_X86_REG_DR3:
|
|
case UC_X86_REG_DR4:
|
|
case UC_X86_REG_DR5:
|
|
case UC_X86_REG_DR6:
|
|
case UC_X86_REG_DR7:
|
|
*(int64_t *)value = X86_CPU(uc, mycpu)->env.dr[regid - UC_X86_REG_DR0];
|
|
break;
|
|
case UC_X86_REG_EFLAGS:
|
|
*(int64_t *)value = cpu_compute_eflags(&X86_CPU(uc, mycpu)->env);
|
|
break;
|
|
case UC_X86_REG_RAX:
|
|
*(uint64_t *)value = X86_CPU(uc, mycpu)->env.regs[R_EAX];
|
|
break;
|
|
case UC_X86_REG_EAX:
|
|
*(int32_t *)value = READ_DWORD(X86_CPU(uc, mycpu)->env.regs[R_EAX]);
|
|
break;
|
|
case UC_X86_REG_AX:
|
|
*(int16_t *)value = READ_WORD(X86_CPU(uc, mycpu)->env.regs[R_EAX]);
|
|
break;
|
|
case UC_X86_REG_AH:
|
|
*(int8_t *)value = READ_BYTE_H(X86_CPU(uc, mycpu)->env.regs[R_EAX]);
|
|
break;
|
|
case UC_X86_REG_AL:
|
|
*(int8_t *)value = READ_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_EAX]);
|
|
break;
|
|
case UC_X86_REG_RBX:
|
|
*(uint64_t *)value = X86_CPU(uc, mycpu)->env.regs[R_EBX];
|
|
break;
|
|
case UC_X86_REG_EBX:
|
|
*(int32_t *)value = READ_DWORD(X86_CPU(uc, mycpu)->env.regs[R_EBX]);
|
|
break;
|
|
case UC_X86_REG_BX:
|
|
*(int16_t *)value = READ_WORD(X86_CPU(uc, mycpu)->env.regs[R_EBX]);
|
|
break;
|
|
case UC_X86_REG_BH:
|
|
*(int8_t *)value = READ_BYTE_H(X86_CPU(uc, mycpu)->env.regs[R_EBX]);
|
|
break;
|
|
case UC_X86_REG_BL:
|
|
*(int8_t *)value = READ_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_EBX]);
|
|
break;
|
|
case UC_X86_REG_RCX:
|
|
*(uint64_t *)value = X86_CPU(uc, mycpu)->env.regs[R_ECX];
|
|
break;
|
|
case UC_X86_REG_ECX:
|
|
*(int32_t *)value = READ_DWORD(X86_CPU(uc, mycpu)->env.regs[R_ECX]);
|
|
break;
|
|
case UC_X86_REG_CX:
|
|
*(int16_t *)value = READ_WORD(X86_CPU(uc, mycpu)->env.regs[R_ECX]);
|
|
break;
|
|
case UC_X86_REG_CH:
|
|
*(int8_t *)value = READ_BYTE_H(X86_CPU(uc, mycpu)->env.regs[R_ECX]);
|
|
break;
|
|
case UC_X86_REG_CL:
|
|
*(int8_t *)value = READ_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_ECX]);
|
|
break;
|
|
case UC_X86_REG_RDX:
|
|
*(uint64_t *)value = X86_CPU(uc, mycpu)->env.regs[R_EDX];
|
|
break;
|
|
case UC_X86_REG_EDX:
|
|
*(int32_t *)value = READ_DWORD(X86_CPU(uc, mycpu)->env.regs[R_EDX]);
|
|
break;
|
|
case UC_X86_REG_DX:
|
|
*(int16_t *)value = READ_WORD(X86_CPU(uc, mycpu)->env.regs[R_EDX]);
|
|
break;
|
|
case UC_X86_REG_DH:
|
|
*(int8_t *)value = READ_BYTE_H(X86_CPU(uc, mycpu)->env.regs[R_EDX]);
|
|
break;
|
|
case UC_X86_REG_DL:
|
|
*(int8_t *)value = READ_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_EDX]);
|
|
break;
|
|
case UC_X86_REG_RSP:
|
|
*(uint64_t *)value = X86_CPU(uc, mycpu)->env.regs[R_ESP];
|
|
break;
|
|
case UC_X86_REG_ESP:
|
|
*(int32_t *)value = READ_DWORD(X86_CPU(uc, mycpu)->env.regs[R_ESP]);
|
|
break;
|
|
case UC_X86_REG_SP:
|
|
*(int16_t *)value = READ_WORD(X86_CPU(uc, mycpu)->env.regs[R_ESP]);
|
|
break;
|
|
case UC_X86_REG_SPL:
|
|
*(int8_t *)value = READ_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_ESP]);
|
|
break;
|
|
case UC_X86_REG_RBP:
|
|
*(uint64_t *)value = X86_CPU(uc, mycpu)->env.regs[R_EBP];
|
|
break;
|
|
case UC_X86_REG_EBP:
|
|
*(int32_t *)value = READ_DWORD(X86_CPU(uc, mycpu)->env.regs[R_EBP]);
|
|
break;
|
|
case UC_X86_REG_BP:
|
|
*(int16_t *)value = READ_WORD(X86_CPU(uc, mycpu)->env.regs[R_EBP]);
|
|
break;
|
|
case UC_X86_REG_BPL:
|
|
*(int8_t *)value = READ_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_EBP]);
|
|
break;
|
|
case UC_X86_REG_RSI:
|
|
*(uint64_t *)value = X86_CPU(uc, mycpu)->env.regs[R_ESI];
|
|
break;
|
|
case UC_X86_REG_ESI:
|
|
*(int32_t *)value = READ_DWORD(X86_CPU(uc, mycpu)->env.regs[R_ESI]);
|
|
break;
|
|
case UC_X86_REG_SI:
|
|
*(int16_t *)value = READ_WORD(X86_CPU(uc, mycpu)->env.regs[R_ESI]);
|
|
break;
|
|
case UC_X86_REG_SIL:
|
|
*(int8_t *)value = READ_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_ESI]);
|
|
break;
|
|
case UC_X86_REG_RDI:
|
|
*(uint64_t *)value = X86_CPU(uc, mycpu)->env.regs[R_EDI];
|
|
break;
|
|
case UC_X86_REG_EDI:
|
|
*(int32_t *)value = READ_DWORD(X86_CPU(uc, mycpu)->env.regs[R_EDI]);
|
|
break;
|
|
case UC_X86_REG_DI:
|
|
*(int16_t *)value = READ_WORD(X86_CPU(uc, mycpu)->env.regs[R_EDI]);
|
|
break;
|
|
case UC_X86_REG_DIL:
|
|
*(int8_t *)value = READ_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_EDI]);
|
|
break;
|
|
case UC_X86_REG_RIP:
|
|
*(uint64_t *)value = X86_CPU(uc, mycpu)->env.eip;
|
|
break;
|
|
case UC_X86_REG_EIP:
|
|
*(int32_t *)value = READ_DWORD(X86_CPU(uc, mycpu)->env.eip);
|
|
break;
|
|
case UC_X86_REG_IP:
|
|
*(int16_t *)value = READ_WORD(X86_CPU(uc, mycpu)->env.eip);
|
|
break;
|
|
case UC_X86_REG_CS:
|
|
*(int16_t *)value = (uint16_t)X86_CPU(uc, mycpu)->env.segs[R_CS].selector;
|
|
break;
|
|
case UC_X86_REG_DS:
|
|
*(int16_t *)value = (uint16_t)X86_CPU(uc, mycpu)->env.segs[R_DS].selector;
|
|
break;
|
|
case UC_X86_REG_SS:
|
|
*(int16_t *)value = (uint16_t)X86_CPU(uc, mycpu)->env.segs[R_SS].selector;
|
|
break;
|
|
case UC_X86_REG_ES:
|
|
*(int16_t *)value = (uint16_t)X86_CPU(uc, mycpu)->env.segs[R_ES].selector;
|
|
break;
|
|
case UC_X86_REG_FS:
|
|
*(int16_t *)value = (uint16_t)X86_CPU(uc, mycpu)->env.segs[R_FS].selector;
|
|
break;
|
|
case UC_X86_REG_GS:
|
|
*(int16_t *)value = (uint16_t)X86_CPU(uc, mycpu)->env.segs[R_GS].selector;
|
|
break;
|
|
case UC_X86_REG_R8:
|
|
*(int64_t *)value = READ_QWORD(X86_CPU(uc, mycpu)->env.regs[8]);
|
|
break;
|
|
case UC_X86_REG_R8D:
|
|
*(int32_t *)value = READ_DWORD(X86_CPU(uc, mycpu)->env.regs[8]);
|
|
break;
|
|
case UC_X86_REG_R8W:
|
|
*(int16_t *)value = READ_WORD(X86_CPU(uc, mycpu)->env.regs[8]);
|
|
break;
|
|
case UC_X86_REG_R8B:
|
|
*(int8_t *)value = READ_BYTE_L(X86_CPU(uc, mycpu)->env.regs[8]);
|
|
break;
|
|
case UC_X86_REG_R9:
|
|
*(int64_t *)value = READ_QWORD(X86_CPU(uc, mycpu)->env.regs[9]);
|
|
break;
|
|
case UC_X86_REG_R9D:
|
|
*(int32_t *)value = READ_DWORD(X86_CPU(uc, mycpu)->env.regs[9]);
|
|
break;
|
|
case UC_X86_REG_R9W:
|
|
*(int16_t *)value = READ_WORD(X86_CPU(uc, mycpu)->env.regs[9]);
|
|
break;
|
|
case UC_X86_REG_R9B:
|
|
*(int8_t *)value = READ_BYTE_L(X86_CPU(uc, mycpu)->env.regs[9]);
|
|
break;
|
|
case UC_X86_REG_R10:
|
|
*(int64_t *)value = READ_QWORD(X86_CPU(uc, mycpu)->env.regs[10]);
|
|
break;
|
|
case UC_X86_REG_R10D:
|
|
*(int32_t *)value = READ_DWORD(X86_CPU(uc, mycpu)->env.regs[10]);
|
|
break;
|
|
case UC_X86_REG_R10W:
|
|
*(int16_t *)value = READ_WORD(X86_CPU(uc, mycpu)->env.regs[10]);
|
|
break;
|
|
case UC_X86_REG_R10B:
|
|
*(int8_t *)value = READ_BYTE_L(X86_CPU(uc, mycpu)->env.regs[10]);
|
|
break;
|
|
case UC_X86_REG_R11:
|
|
*(int64_t *)value = READ_QWORD(X86_CPU(uc, mycpu)->env.regs[11]);
|
|
break;
|
|
case UC_X86_REG_R11D:
|
|
*(int32_t *)value = READ_DWORD(X86_CPU(uc, mycpu)->env.regs[11]);
|
|
break;
|
|
case UC_X86_REG_R11W:
|
|
*(int16_t *)value = READ_WORD(X86_CPU(uc, mycpu)->env.regs[11]);
|
|
break;
|
|
case UC_X86_REG_R11B:
|
|
*(int8_t *)value = READ_BYTE_L(X86_CPU(uc, mycpu)->env.regs[11]);
|
|
break;
|
|
case UC_X86_REG_R12:
|
|
*(int64_t *)value = READ_QWORD(X86_CPU(uc, mycpu)->env.regs[12]);
|
|
break;
|
|
case UC_X86_REG_R12D:
|
|
*(int32_t *)value = READ_DWORD(X86_CPU(uc, mycpu)->env.regs[12]);
|
|
break;
|
|
case UC_X86_REG_R12W:
|
|
*(int16_t *)value = READ_WORD(X86_CPU(uc, mycpu)->env.regs[12]);
|
|
break;
|
|
case UC_X86_REG_R12B:
|
|
*(int8_t *)value = READ_BYTE_L(X86_CPU(uc, mycpu)->env.regs[12]);
|
|
break;
|
|
case UC_X86_REG_R13:
|
|
*(int64_t *)value = READ_QWORD(X86_CPU(uc, mycpu)->env.regs[13]);
|
|
break;
|
|
case UC_X86_REG_R13D:
|
|
*(int32_t *)value = READ_DWORD(X86_CPU(uc, mycpu)->env.regs[13]);
|
|
break;
|
|
case UC_X86_REG_R13W:
|
|
*(int16_t *)value = READ_WORD(X86_CPU(uc, mycpu)->env.regs[13]);
|
|
break;
|
|
case UC_X86_REG_R13B:
|
|
*(int8_t *)value = READ_BYTE_L(X86_CPU(uc, mycpu)->env.regs[13]);
|
|
break;
|
|
case UC_X86_REG_R14:
|
|
*(int64_t *)value = READ_QWORD(X86_CPU(uc, mycpu)->env.regs[14]);
|
|
break;
|
|
case UC_X86_REG_R14D:
|
|
*(int32_t *)value = READ_DWORD(X86_CPU(uc, mycpu)->env.regs[14]);
|
|
break;
|
|
case UC_X86_REG_R14W:
|
|
*(int16_t *)value = READ_WORD(X86_CPU(uc, mycpu)->env.regs[14]);
|
|
break;
|
|
case UC_X86_REG_R14B:
|
|
*(int8_t *)value = READ_BYTE_L(X86_CPU(uc, mycpu)->env.regs[14]);
|
|
break;
|
|
case UC_X86_REG_R15:
|
|
*(int64_t *)value = READ_QWORD(X86_CPU(uc, mycpu)->env.regs[15]);
|
|
break;
|
|
case UC_X86_REG_R15D:
|
|
*(int32_t *)value = READ_DWORD(X86_CPU(uc, mycpu)->env.regs[15]);
|
|
break;
|
|
case UC_X86_REG_R15W:
|
|
*(int16_t *)value = READ_WORD(X86_CPU(uc, mycpu)->env.regs[15]);
|
|
break;
|
|
case UC_X86_REG_R15B:
|
|
*(int8_t *)value = READ_BYTE_L(X86_CPU(uc, mycpu)->env.regs[15]);
|
|
break;
|
|
case UC_X86_REG_IDTR:
|
|
((uc_x86_mmr *)value)->limit = (uint16_t)X86_CPU(uc, mycpu)->env.idt.limit;
|
|
((uc_x86_mmr *)value)->base = X86_CPU(uc, mycpu)->env.idt.base;
|
|
break;
|
|
case UC_X86_REG_GDTR:
|
|
((uc_x86_mmr *)value)->limit = (uint16_t)X86_CPU(uc, mycpu)->env.gdt.limit;
|
|
((uc_x86_mmr *)value)->base = X86_CPU(uc, mycpu)->env.gdt.base;
|
|
break;
|
|
case UC_X86_REG_LDTR:
|
|
((uc_x86_mmr *)value)->limit = X86_CPU(uc, mycpu)->env.ldt.limit;
|
|
((uc_x86_mmr *)value)->base = X86_CPU(uc, mycpu)->env.ldt.base;
|
|
((uc_x86_mmr *)value)->selector = (uint16_t)X86_CPU(uc, mycpu)->env.ldt.selector;
|
|
((uc_x86_mmr *)value)->flags = X86_CPU(uc, mycpu)->env.ldt.flags;
|
|
break;
|
|
case UC_X86_REG_TR:
|
|
((uc_x86_mmr *)value)->limit = X86_CPU(uc, mycpu)->env.tr.limit;
|
|
((uc_x86_mmr *)value)->base = X86_CPU(uc, mycpu)->env.tr.base;
|
|
((uc_x86_mmr *)value)->selector = (uint16_t)X86_CPU(uc, mycpu)->env.tr.selector;
|
|
((uc_x86_mmr *)value)->flags = X86_CPU(uc, mycpu)->env.tr.flags;
|
|
break;
|
|
case UC_X86_REG_MSR:
|
|
x86_msr_read(uc, (uc_x86_msr *)value);
|
|
break;
|
|
}
|
|
break;
|
|
#endif
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int x86_reg_write(struct uc_struct *uc, unsigned int *regs, void *const *vals, int count)
|
|
{
|
|
CPUState *mycpu = uc->cpu;
|
|
int i;
|
|
|
|
for (i = 0; i < count; i++) {
|
|
unsigned int regid = regs[i];
|
|
const void *value = vals[i];
|
|
switch(regid) {
|
|
default:
|
|
break;
|
|
case UC_X86_REG_FP0:
|
|
case UC_X86_REG_FP1:
|
|
case UC_X86_REG_FP2:
|
|
case UC_X86_REG_FP3:
|
|
case UC_X86_REG_FP4:
|
|
case UC_X86_REG_FP5:
|
|
case UC_X86_REG_FP6:
|
|
case UC_X86_REG_FP7:
|
|
{
|
|
uint64_t mant = *(uint64_t*) value;
|
|
uint16_t upper = *(uint16_t*) ((char*)value + sizeof(uint64_t));
|
|
X86_CPU(uc, mycpu)->env.fpregs[regid - UC_X86_REG_FP0].d = cpu_set_fp80(mant, upper);
|
|
}
|
|
continue;
|
|
case UC_X86_REG_FPSW:
|
|
{
|
|
uint16_t fpus = *(uint16_t*) value;
|
|
X86_CPU(uc, mycpu)->env.fpus = fpus & ~0x3800;
|
|
X86_CPU(uc, mycpu)->env.fpstt = (fpus >> 11) & 0x7;
|
|
}
|
|
continue;
|
|
case UC_X86_REG_FPCW:
|
|
X86_CPU(uc, mycpu)->env.fpuc = *(uint16_t *)value;
|
|
continue;
|
|
case UC_X86_REG_FPTAG:
|
|
{
|
|
int i;
|
|
uint16_t fptag = *(uint16_t*) value;
|
|
for (i = 0; i < 8; i++) {
|
|
X86_CPU(uc, mycpu)->env.fptags[i] = ((fptag & 3) == 3);
|
|
fptag >>= 2;
|
|
}
|
|
|
|
continue;
|
|
}
|
|
break;
|
|
case UC_X86_REG_XMM0:
|
|
case UC_X86_REG_XMM1:
|
|
case UC_X86_REG_XMM2:
|
|
case UC_X86_REG_XMM3:
|
|
case UC_X86_REG_XMM4:
|
|
case UC_X86_REG_XMM5:
|
|
case UC_X86_REG_XMM6:
|
|
case UC_X86_REG_XMM7:
|
|
{
|
|
float64 *src = (float64*)value;
|
|
XMMReg *reg = &X86_CPU(uc, mycpu)->env.xmm_regs[regid - UC_X86_REG_XMM0];
|
|
reg->XMM_D(0) = src[0];
|
|
reg->XMM_D(1) = src[1];
|
|
continue;
|
|
}
|
|
case UC_X86_REG_YMM0:
|
|
case UC_X86_REG_YMM1:
|
|
case UC_X86_REG_YMM2:
|
|
case UC_X86_REG_YMM3:
|
|
case UC_X86_REG_YMM4:
|
|
case UC_X86_REG_YMM5:
|
|
case UC_X86_REG_YMM6:
|
|
case UC_X86_REG_YMM7:
|
|
{
|
|
float64 *src = (float64*)value;
|
|
XMMReg *reg = &X86_CPU(uc, mycpu)->env.xmm_regs[regid - UC_X86_REG_XMM0];
|
|
reg->XMM_D(4) = src[0];
|
|
reg->XMM_D(5) = src[1];
|
|
reg->XMM_D(6) = src[2];
|
|
reg->XMM_D(7) = src[3];
|
|
continue;
|
|
}
|
|
}
|
|
|
|
switch(uc->mode) {
|
|
default:
|
|
break;
|
|
|
|
case UC_MODE_16:
|
|
switch(regid) {
|
|
default: break;
|
|
case UC_X86_REG_ES:
|
|
load_seg_16_helper(&X86_CPU(uc, mycpu)->env, R_ES, *(uint16_t *)value);
|
|
continue;
|
|
case UC_X86_REG_SS:
|
|
load_seg_16_helper(&X86_CPU(uc, mycpu)->env, R_SS, *(uint16_t *)value);
|
|
continue;
|
|
case UC_X86_REG_DS:
|
|
load_seg_16_helper(&X86_CPU(uc, mycpu)->env, R_DS, *(uint16_t *)value);
|
|
continue;
|
|
case UC_X86_REG_FS:
|
|
load_seg_16_helper(&X86_CPU(uc, mycpu)->env, R_FS, *(uint16_t *)value);
|
|
continue;
|
|
case UC_X86_REG_GS:
|
|
load_seg_16_helper(&X86_CPU(uc, mycpu)->env, R_GS, *(uint16_t *)value);
|
|
continue;
|
|
}
|
|
// fall-thru
|
|
case UC_MODE_32:
|
|
switch(regid) {
|
|
default:
|
|
break;
|
|
case UC_X86_REG_CR0:
|
|
case UC_X86_REG_CR1:
|
|
case UC_X86_REG_CR2:
|
|
case UC_X86_REG_CR3:
|
|
case UC_X86_REG_CR4:
|
|
X86_CPU(uc, mycpu)->env.cr[regid - UC_X86_REG_CR0] = *(uint32_t *)value;
|
|
break;
|
|
case UC_X86_REG_DR0:
|
|
case UC_X86_REG_DR1:
|
|
case UC_X86_REG_DR2:
|
|
case UC_X86_REG_DR3:
|
|
case UC_X86_REG_DR4:
|
|
case UC_X86_REG_DR5:
|
|
case UC_X86_REG_DR6:
|
|
case UC_X86_REG_DR7:
|
|
X86_CPU(uc, mycpu)->env.dr[regid - UC_X86_REG_DR0] = *(uint32_t *)value;
|
|
break;
|
|
case UC_X86_REG_EFLAGS:
|
|
cpu_load_eflags(&X86_CPU(uc, mycpu)->env, *(uint32_t *)value, -1);
|
|
X86_CPU(uc, mycpu)->env.eflags0 = *(uint32_t *)value;
|
|
break;
|
|
case UC_X86_REG_EAX:
|
|
X86_CPU(uc, mycpu)->env.regs[R_EAX] = *(uint32_t *)value;
|
|
break;
|
|
case UC_X86_REG_AX:
|
|
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_EAX], *(uint16_t *)value);
|
|
break;
|
|
case UC_X86_REG_AH:
|
|
WRITE_BYTE_H(X86_CPU(uc, mycpu)->env.regs[R_EAX], *(uint8_t *)value);
|
|
break;
|
|
case UC_X86_REG_AL:
|
|
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_EAX], *(uint8_t *)value);
|
|
break;
|
|
case UC_X86_REG_EBX:
|
|
X86_CPU(uc, mycpu)->env.regs[R_EBX] = *(uint32_t *)value;
|
|
break;
|
|
case UC_X86_REG_BX:
|
|
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_EBX], *(uint16_t *)value);
|
|
break;
|
|
case UC_X86_REG_BH:
|
|
WRITE_BYTE_H(X86_CPU(uc, mycpu)->env.regs[R_EBX], *(uint8_t *)value);
|
|
break;
|
|
case UC_X86_REG_BL:
|
|
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_EBX], *(uint8_t *)value);
|
|
break;
|
|
case UC_X86_REG_ECX:
|
|
X86_CPU(uc, mycpu)->env.regs[R_ECX] = *(uint32_t *)value;
|
|
break;
|
|
case UC_X86_REG_CX:
|
|
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_ECX], *(uint16_t *)value);
|
|
break;
|
|
case UC_X86_REG_CH:
|
|
WRITE_BYTE_H(X86_CPU(uc, mycpu)->env.regs[R_ECX], *(uint8_t *)value);
|
|
break;
|
|
case UC_X86_REG_CL:
|
|
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_ECX], *(uint8_t *)value);
|
|
break;
|
|
case UC_X86_REG_EDX:
|
|
X86_CPU(uc, mycpu)->env.regs[R_EDX] = *(uint32_t *)value;
|
|
break;
|
|
case UC_X86_REG_DX:
|
|
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_EDX], *(uint16_t *)value);
|
|
break;
|
|
case UC_X86_REG_DH:
|
|
WRITE_BYTE_H(X86_CPU(uc, mycpu)->env.regs[R_EDX], *(uint8_t *)value);
|
|
break;
|
|
case UC_X86_REG_DL:
|
|
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_EDX], *(uint8_t *)value);
|
|
break;
|
|
case UC_X86_REG_ESP:
|
|
X86_CPU(uc, mycpu)->env.regs[R_ESP] = *(uint32_t *)value;
|
|
break;
|
|
case UC_X86_REG_SP:
|
|
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_ESP], *(uint16_t *)value);
|
|
break;
|
|
case UC_X86_REG_EBP:
|
|
X86_CPU(uc, mycpu)->env.regs[R_EBP] = *(uint32_t *)value;
|
|
break;
|
|
case UC_X86_REG_BP:
|
|
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_EBP], *(uint16_t *)value);
|
|
break;
|
|
case UC_X86_REG_ESI:
|
|
X86_CPU(uc, mycpu)->env.regs[R_ESI] = *(uint32_t *)value;
|
|
break;
|
|
case UC_X86_REG_SI:
|
|
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_ESI], *(uint16_t *)value);
|
|
break;
|
|
case UC_X86_REG_EDI:
|
|
X86_CPU(uc, mycpu)->env.regs[R_EDI] = *(uint32_t *)value;
|
|
break;
|
|
case UC_X86_REG_DI:
|
|
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_EDI], *(uint16_t *)value);
|
|
break;
|
|
case UC_X86_REG_EIP:
|
|
X86_CPU(uc, mycpu)->env.eip = *(uint32_t *)value;
|
|
// force to quit execution and flush TB
|
|
uc->quit_request = true;
|
|
uc_emu_stop(uc);
|
|
break;
|
|
case UC_X86_REG_IP:
|
|
WRITE_WORD(X86_CPU(uc, mycpu)->env.eip, *(uint16_t *)value);
|
|
// force to quit execution and flush TB
|
|
uc->quit_request = true;
|
|
uc_emu_stop(uc);
|
|
break;
|
|
case UC_X86_REG_CS:
|
|
cpu_x86_load_seg(&X86_CPU(uc, mycpu)->env, R_CS, *(uint16_t *)value);
|
|
break;
|
|
case UC_X86_REG_DS:
|
|
cpu_x86_load_seg(&X86_CPU(uc, mycpu)->env, R_DS, *(uint16_t *)value);
|
|
break;
|
|
case UC_X86_REG_SS:
|
|
cpu_x86_load_seg(&X86_CPU(uc, mycpu)->env, R_SS, *(uint16_t *)value);
|
|
break;
|
|
case UC_X86_REG_ES:
|
|
cpu_x86_load_seg(&X86_CPU(uc, mycpu)->env, R_ES, *(uint16_t *)value);
|
|
break;
|
|
case UC_X86_REG_FS:
|
|
cpu_x86_load_seg(&X86_CPU(uc, mycpu)->env, R_FS, *(uint16_t *)value);
|
|
break;
|
|
case UC_X86_REG_GS:
|
|
cpu_x86_load_seg(&X86_CPU(uc, mycpu)->env, R_GS, *(uint16_t *)value);
|
|
break;
|
|
case UC_X86_REG_IDTR:
|
|
X86_CPU(uc, mycpu)->env.idt.limit = (uint16_t)((uc_x86_mmr *)value)->limit;
|
|
X86_CPU(uc, mycpu)->env.idt.base = (uint32_t)((uc_x86_mmr *)value)->base;
|
|
break;
|
|
case UC_X86_REG_GDTR:
|
|
X86_CPU(uc, mycpu)->env.gdt.limit = (uint16_t)((uc_x86_mmr *)value)->limit;
|
|
X86_CPU(uc, mycpu)->env.gdt.base = (uint32_t)((uc_x86_mmr *)value)->base;
|
|
break;
|
|
case UC_X86_REG_LDTR:
|
|
X86_CPU(uc, mycpu)->env.ldt.limit = ((uc_x86_mmr *)value)->limit;
|
|
X86_CPU(uc, mycpu)->env.ldt.base = (uint32_t)((uc_x86_mmr *)value)->base;
|
|
X86_CPU(uc, mycpu)->env.ldt.selector = (uint16_t)((uc_x86_mmr *)value)->selector;
|
|
X86_CPU(uc, mycpu)->env.ldt.flags = ((uc_x86_mmr *)value)->flags;
|
|
break;
|
|
case UC_X86_REG_TR:
|
|
X86_CPU(uc, mycpu)->env.tr.limit = ((uc_x86_mmr *)value)->limit;
|
|
X86_CPU(uc, mycpu)->env.tr.base = (uint32_t)((uc_x86_mmr *)value)->base;
|
|
X86_CPU(uc, mycpu)->env.tr.selector = (uint16_t)((uc_x86_mmr *)value)->selector;
|
|
X86_CPU(uc, mycpu)->env.tr.flags = ((uc_x86_mmr *)value)->flags;
|
|
break;
|
|
case UC_X86_REG_MSR:
|
|
x86_msr_write(uc, (uc_x86_msr *)value);
|
|
break;
|
|
}
|
|
break;
|
|
|
|
#ifdef TARGET_X86_64
|
|
case UC_MODE_64:
|
|
switch(regid) {
|
|
default:
|
|
break;
|
|
case UC_X86_REG_CR0:
|
|
case UC_X86_REG_CR1:
|
|
case UC_X86_REG_CR2:
|
|
case UC_X86_REG_CR3:
|
|
case UC_X86_REG_CR4:
|
|
X86_CPU(uc, mycpu)->env.cr[regid - UC_X86_REG_CR0] = *(uint64_t *)value;
|
|
break;
|
|
case UC_X86_REG_DR0:
|
|
case UC_X86_REG_DR1:
|
|
case UC_X86_REG_DR2:
|
|
case UC_X86_REG_DR3:
|
|
case UC_X86_REG_DR4:
|
|
case UC_X86_REG_DR5:
|
|
case UC_X86_REG_DR6:
|
|
case UC_X86_REG_DR7:
|
|
X86_CPU(uc, mycpu)->env.dr[regid - UC_X86_REG_DR0] = *(uint64_t *)value;
|
|
break;
|
|
case UC_X86_REG_EFLAGS:
|
|
cpu_load_eflags(&X86_CPU(uc, mycpu)->env, *(uint64_t *)value, -1);
|
|
X86_CPU(uc, mycpu)->env.eflags0 = *(uint64_t *)value;
|
|
break;
|
|
case UC_X86_REG_RAX:
|
|
X86_CPU(uc, mycpu)->env.regs[R_EAX] = *(uint64_t *)value;
|
|
break;
|
|
case UC_X86_REG_EAX:
|
|
WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[R_EAX], *(uint32_t *)value);
|
|
break;
|
|
case UC_X86_REG_AX:
|
|
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_EAX], *(uint16_t *)value);
|
|
break;
|
|
case UC_X86_REG_AH:
|
|
WRITE_BYTE_H(X86_CPU(uc, mycpu)->env.regs[R_EAX], *(uint8_t *)value);
|
|
break;
|
|
case UC_X86_REG_AL:
|
|
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_EAX], *(uint8_t *)value);
|
|
break;
|
|
case UC_X86_REG_RBX:
|
|
X86_CPU(uc, mycpu)->env.regs[R_EBX] = *(uint64_t *)value;
|
|
break;
|
|
case UC_X86_REG_EBX:
|
|
WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[R_EBX], *(uint32_t *)value);
|
|
break;
|
|
case UC_X86_REG_BX:
|
|
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_EBX], *(uint16_t *)value);
|
|
break;
|
|
case UC_X86_REG_BH:
|
|
WRITE_BYTE_H(X86_CPU(uc, mycpu)->env.regs[R_EBX], *(uint8_t *)value);
|
|
break;
|
|
case UC_X86_REG_BL:
|
|
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_EBX], *(uint8_t *)value);
|
|
break;
|
|
case UC_X86_REG_RCX:
|
|
X86_CPU(uc, mycpu)->env.regs[R_ECX] = *(uint64_t *)value;
|
|
break;
|
|
case UC_X86_REG_ECX:
|
|
WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[R_ECX], *(uint32_t *)value);
|
|
break;
|
|
case UC_X86_REG_CX:
|
|
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_ECX], *(uint16_t *)value);
|
|
break;
|
|
case UC_X86_REG_CH:
|
|
WRITE_BYTE_H(X86_CPU(uc, mycpu)->env.regs[R_ECX], *(uint8_t *)value);
|
|
break;
|
|
case UC_X86_REG_CL:
|
|
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_ECX], *(uint8_t *)value);
|
|
break;
|
|
case UC_X86_REG_RDX:
|
|
X86_CPU(uc, mycpu)->env.regs[R_EDX] = *(uint64_t *)value;
|
|
break;
|
|
case UC_X86_REG_EDX:
|
|
WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[R_EDX], *(uint32_t *)value);
|
|
break;
|
|
case UC_X86_REG_DX:
|
|
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_EDX], *(uint16_t *)value);
|
|
break;
|
|
case UC_X86_REG_DH:
|
|
WRITE_BYTE_H(X86_CPU(uc, mycpu)->env.regs[R_EDX], *(uint8_t *)value);
|
|
break;
|
|
case UC_X86_REG_DL:
|
|
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_EDX], *(uint8_t *)value);
|
|
break;
|
|
case UC_X86_REG_RSP:
|
|
X86_CPU(uc, mycpu)->env.regs[R_ESP] = *(uint64_t *)value;
|
|
break;
|
|
case UC_X86_REG_ESP:
|
|
WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[R_ESP], *(uint32_t *)value);
|
|
break;
|
|
case UC_X86_REG_SP:
|
|
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_ESP], *(uint16_t *)value);
|
|
break;
|
|
case UC_X86_REG_SPL:
|
|
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_ESP], *(uint8_t *)value);
|
|
break;
|
|
case UC_X86_REG_RBP:
|
|
X86_CPU(uc, mycpu)->env.regs[R_EBP] = *(uint64_t *)value;
|
|
break;
|
|
case UC_X86_REG_EBP:
|
|
WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[R_EBP], *(uint32_t *)value);
|
|
break;
|
|
case UC_X86_REG_BP:
|
|
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_EBP], *(uint16_t *)value);
|
|
break;
|
|
case UC_X86_REG_BPL:
|
|
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_EBP], *(uint8_t *)value);
|
|
break;
|
|
case UC_X86_REG_RSI:
|
|
X86_CPU(uc, mycpu)->env.regs[R_ESI] = *(uint64_t *)value;
|
|
break;
|
|
case UC_X86_REG_ESI:
|
|
WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[R_ESI], *(uint32_t *)value);
|
|
break;
|
|
case UC_X86_REG_SI:
|
|
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_ESI], *(uint16_t *)value);
|
|
break;
|
|
case UC_X86_REG_SIL:
|
|
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_ESI], *(uint8_t *)value);
|
|
break;
|
|
case UC_X86_REG_RDI:
|
|
X86_CPU(uc, mycpu)->env.regs[R_EDI] = *(uint64_t *)value;
|
|
break;
|
|
case UC_X86_REG_EDI:
|
|
WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[R_EDI], *(uint32_t *)value);
|
|
break;
|
|
case UC_X86_REG_DI:
|
|
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_EDI], *(uint16_t *)value);
|
|
break;
|
|
case UC_X86_REG_DIL:
|
|
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_EDI], *(uint8_t *)value);
|
|
break;
|
|
case UC_X86_REG_RIP:
|
|
X86_CPU(uc, mycpu)->env.eip = *(uint64_t *)value;
|
|
// force to quit execution and flush TB
|
|
uc->quit_request = true;
|
|
uc_emu_stop(uc);
|
|
break;
|
|
case UC_X86_REG_EIP:
|
|
WRITE_DWORD(X86_CPU(uc, mycpu)->env.eip, *(uint32_t *)value);
|
|
// force to quit execution and flush TB
|
|
uc->quit_request = true;
|
|
uc_emu_stop(uc);
|
|
break;
|
|
case UC_X86_REG_IP:
|
|
WRITE_WORD(X86_CPU(uc, mycpu)->env.eip, *(uint16_t *)value);
|
|
// force to quit execution and flush TB
|
|
uc->quit_request = true;
|
|
uc_emu_stop(uc);
|
|
break;
|
|
case UC_X86_REG_CS:
|
|
X86_CPU(uc, mycpu)->env.segs[R_CS].selector = *(uint16_t *)value;
|
|
break;
|
|
case UC_X86_REG_DS:
|
|
X86_CPU(uc, mycpu)->env.segs[R_DS].selector = *(uint16_t *)value;
|
|
break;
|
|
case UC_X86_REG_SS:
|
|
X86_CPU(uc, mycpu)->env.segs[R_SS].selector = *(uint16_t *)value;
|
|
break;
|
|
case UC_X86_REG_ES:
|
|
X86_CPU(uc, mycpu)->env.segs[R_ES].selector = *(uint16_t *)value;
|
|
break;
|
|
case UC_X86_REG_FS:
|
|
X86_CPU(uc, mycpu)->env.segs[R_FS].selector = *(uint16_t *)value;
|
|
break;
|
|
case UC_X86_REG_GS:
|
|
X86_CPU(uc, mycpu)->env.segs[R_GS].selector = *(uint16_t *)value;
|
|
break;
|
|
case UC_X86_REG_R8:
|
|
X86_CPU(uc, mycpu)->env.regs[8] = *(uint64_t *)value;
|
|
break;
|
|
case UC_X86_REG_R8D:
|
|
WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[8], *(uint32_t *)value);
|
|
break;
|
|
case UC_X86_REG_R8W:
|
|
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[8], *(uint16_t *)value);
|
|
break;
|
|
case UC_X86_REG_R8B:
|
|
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[8], *(uint8_t *)value);
|
|
break;
|
|
case UC_X86_REG_R9:
|
|
X86_CPU(uc, mycpu)->env.regs[9] = *(uint64_t *)value;
|
|
break;
|
|
case UC_X86_REG_R9D:
|
|
WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[9], *(uint32_t *)value);
|
|
break;
|
|
case UC_X86_REG_R9W:
|
|
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[9], *(uint16_t *)value);
|
|
break;
|
|
case UC_X86_REG_R9B:
|
|
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[9], *(uint8_t *)value);
|
|
break;
|
|
case UC_X86_REG_R10:
|
|
X86_CPU(uc, mycpu)->env.regs[10] = *(uint64_t *)value;
|
|
break;
|
|
case UC_X86_REG_R10D:
|
|
WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[10], *(uint32_t *)value);
|
|
break;
|
|
case UC_X86_REG_R10W:
|
|
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[10], *(uint16_t *)value);
|
|
break;
|
|
case UC_X86_REG_R10B:
|
|
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[10], *(uint8_t *)value);
|
|
break;
|
|
case UC_X86_REG_R11:
|
|
X86_CPU(uc, mycpu)->env.regs[11] = *(uint64_t *)value;
|
|
break;
|
|
case UC_X86_REG_R11D:
|
|
WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[11], *(uint32_t *)value);
|
|
break;
|
|
case UC_X86_REG_R11W:
|
|
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[11], *(uint16_t *)value);
|
|
break;
|
|
case UC_X86_REG_R11B:
|
|
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[11], *(uint8_t *)value);
|
|
break;
|
|
case UC_X86_REG_R12:
|
|
X86_CPU(uc, mycpu)->env.regs[12] = *(uint64_t *)value;
|
|
break;
|
|
case UC_X86_REG_R12D:
|
|
WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[12], *(uint32_t *)value);
|
|
break;
|
|
case UC_X86_REG_R12W:
|
|
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[12], *(uint16_t *)value);
|
|
break;
|
|
case UC_X86_REG_R12B:
|
|
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[12], *(uint8_t *)value);
|
|
break;
|
|
case UC_X86_REG_R13:
|
|
X86_CPU(uc, mycpu)->env.regs[13] = *(uint64_t *)value;
|
|
break;
|
|
case UC_X86_REG_R13D:
|
|
WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[13], *(uint32_t *)value);
|
|
break;
|
|
case UC_X86_REG_R13W:
|
|
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[13], *(uint16_t *)value);
|
|
break;
|
|
case UC_X86_REG_R13B:
|
|
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[13], *(uint8_t *)value);
|
|
break;
|
|
case UC_X86_REG_R14:
|
|
X86_CPU(uc, mycpu)->env.regs[14] = *(uint64_t *)value;
|
|
break;
|
|
case UC_X86_REG_R14D:
|
|
WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[14], *(uint32_t *)value);
|
|
break;
|
|
case UC_X86_REG_R14W:
|
|
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[14], *(uint16_t *)value);
|
|
break;
|
|
case UC_X86_REG_R14B:
|
|
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[14], *(uint8_t *)value);
|
|
break;
|
|
case UC_X86_REG_R15:
|
|
X86_CPU(uc, mycpu)->env.regs[15] = *(uint64_t *)value;
|
|
break;
|
|
case UC_X86_REG_R15D:
|
|
WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[15], *(uint32_t *)value);
|
|
break;
|
|
case UC_X86_REG_R15W:
|
|
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[15], *(uint16_t *)value);
|
|
break;
|
|
case UC_X86_REG_R15B:
|
|
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[15], *(uint8_t *)value);
|
|
break;
|
|
case UC_X86_REG_IDTR:
|
|
X86_CPU(uc, mycpu)->env.idt.limit = (uint16_t)((uc_x86_mmr *)value)->limit;
|
|
X86_CPU(uc, mycpu)->env.idt.base = ((uc_x86_mmr *)value)->base;
|
|
break;
|
|
case UC_X86_REG_GDTR:
|
|
X86_CPU(uc, mycpu)->env.gdt.limit = (uint16_t)((uc_x86_mmr *)value)->limit;
|
|
X86_CPU(uc, mycpu)->env.gdt.base = ((uc_x86_mmr *)value)->base;
|
|
break;
|
|
case UC_X86_REG_LDTR:
|
|
X86_CPU(uc, mycpu)->env.ldt.limit = ((uc_x86_mmr *)value)->limit;
|
|
X86_CPU(uc, mycpu)->env.ldt.base = ((uc_x86_mmr *)value)->base;
|
|
X86_CPU(uc, mycpu)->env.ldt.selector = (uint16_t)((uc_x86_mmr *)value)->selector;
|
|
X86_CPU(uc, mycpu)->env.ldt.flags = ((uc_x86_mmr *)value)->flags;
|
|
break;
|
|
case UC_X86_REG_TR:
|
|
X86_CPU(uc, mycpu)->env.tr.limit = ((uc_x86_mmr *)value)->limit;
|
|
X86_CPU(uc, mycpu)->env.tr.base = ((uc_x86_mmr *)value)->base;
|
|
X86_CPU(uc, mycpu)->env.tr.selector = (uint16_t)((uc_x86_mmr *)value)->selector;
|
|
X86_CPU(uc, mycpu)->env.tr.flags = ((uc_x86_mmr *)value)->flags;
|
|
break;
|
|
case UC_X86_REG_MSR:
|
|
x86_msr_write(uc, (uc_x86_msr *)value);
|
|
break;
|
|
}
|
|
break;
|
|
#endif
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
DEFAULT_VISIBILITY
|
|
int x86_uc_machine_init(struct uc_struct *uc)
|
|
{
|
|
return machine_initialize(uc);
|
|
}
|
|
|
|
static bool x86_stop_interrupt(int intno)
|
|
{
|
|
switch(intno) {
|
|
default:
|
|
return false;
|
|
case EXCP06_ILLOP:
|
|
return true;
|
|
}
|
|
}
|
|
|
|
void pc_machine_init(struct uc_struct *uc);
|
|
|
|
static bool x86_insn_hook_validate(uint32_t insn_enum)
|
|
{
|
|
//for x86 we can only hook IN, OUT, and SYSCALL
|
|
if (insn_enum != UC_X86_INS_IN
|
|
&& insn_enum != UC_X86_INS_OUT
|
|
&& insn_enum != UC_X86_INS_SYSCALL) {
|
|
return false;
|
|
}
|
|
return true;
|
|
}
|
|
|
|
DEFAULT_VISIBILITY
|
|
void x86_uc_init(struct uc_struct* uc)
|
|
{
|
|
apic_register_types(uc);
|
|
apic_common_register_types(uc);
|
|
register_accel_types(uc);
|
|
pc_machine_register_types(uc);
|
|
x86_cpu_register_types(uc);
|
|
pc_machine_init(uc); // pc_piix
|
|
uc->reg_read = x86_reg_read;
|
|
uc->reg_write = x86_reg_write;
|
|
uc->reg_reset = x86_reg_reset;
|
|
uc->release = x86_release;
|
|
uc->set_pc = x86_set_pc;
|
|
uc->stop_interrupt = x86_stop_interrupt;
|
|
uc->insn_hook_validate = x86_insn_hook_validate;
|
|
uc_common_init(uc);
|
|
}
|
|
|
|
/* vim: set ts=4 sts=4 sw=4 et: */
|