Sergey Sorokin c05902eddd target-arm: Fix TTBR selecting logic on AArch32 Stage 2 translation ... Address size is 40-bit for the AArch32 stage 2 translation, and t0sz can be negative (from -8 to 7), so we need to adjust it to use the existing TTBR selecting logic. Backports commit 6e99f762612827afeff54add2e4fc2c3b2657fed from qemu		2018-02-24 16:54:32 -05:00
..
arm_ldst.h	cpu: move exec-all.h inclusion out of cpu.h	2018-02-24 02:39:08 -05:00
cpu-qom.h	target-arm: make cpu-qom.h not target specific	2018-02-24 00:48:59 -05:00
cpu.c	cpu: move exec-all.h inclusion out of cpu.h	2018-02-24 02:39:08 -05:00
cpu.h	target-arm: A64: Create Instruction Syndromes for Data Aborts	2018-02-24 16:46:44 -05:00
cpu64.c	target-arm: Get rid of unused variable warnings	2018-02-23 12:43:09 -05:00
crypto_helper.c
helper-a64.c	cpu: move exec-all.h inclusion out of cpu.h	2018-02-24 02:39:08 -05:00
helper-a64.h
helper.c	target-arm: Fix TTBR selecting logic on AArch32 Stage 2 translation	2018-02-24 16:54:32 -05:00
helper.h	target-arm: Implement MRS (banked) and MSR (banked) instructions	2018-02-21 21:50:42 -05:00
internals.h	target-arm: Set IL bit in syndromes for insn abort, watchpoint, swstep	2018-02-24 16:48:59 -05:00
iwmmxt_helper.c
kvm-consts.h
Makefile.objs
neon_helper.c
op_addsub.h
op_helper.c	target-arm: A64: Create Instruction Syndromes for Data Aborts	2018-02-24 16:46:44 -05:00
psci.c	cpu: move exec-all.h inclusion out of cpu.h	2018-02-24 02:39:08 -05:00
translate-a64.c	target-arm: A64: Create Instruction Syndromes for Data Aborts	2018-02-24 16:46:44 -05:00
translate.c	target-arm: A64: Create Instruction Syndromes for Data Aborts	2018-02-24 16:46:44 -05:00
translate.h	target-arm: A64: Create Instruction Syndromes for Data Aborts	2018-02-24 16:46:44 -05:00
unicorn.h
unicorn_aarch64.c	qemu-common: push cpu.h inclusion out of qemu-common.h	2018-02-24 01:50:56 -05:00
unicorn_arm.c	qemu-common: push cpu.h inclusion out of qemu-common.h	2018-02-24 01:50:56 -05:00