Lioncash b6f752970b target/riscv: Initial introduction of the RISC-V target ... This ports over the RISC-V architecture from Qemu. This is currently a very barebones transition. No code hooking or any fancy stuff. Currently, you can feed it instructions and query the CPU state itself. This also allows choosing whether or not RISC-V 32-bit or RISC-V 64-bit is desirable through Unicorn's interface as well. Extremely basic examples of executing a single instruction have been added to the samples directory to help demonstrate how to use the basic functionality.		2019-03-08 21:46:10 -05:00
..
.gitignore
Makefile	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00
mem_apis.c
sample_all.sh	Added arm64eb sample to sample_all.sh script (#809)	2017-04-25 13:42:13 +08:00
sample_arm.c
sample_arm64.c	Fixed register mistake in comments (#894)	2017-09-17 16:40:01 +07:00
sample_arm64eb.c	arm64eb: arm64 big endian also using little endian instructions. (#816)	2017-05-04 20:00:48 +08:00
sample_armeb.c	update armeb & arm64eb samples	2017-04-25 12:55:26 +08:00
sample_batch_reg.c
sample_m68k.c
sample_mips.c
sample_riscv.c	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00
sample_sparc.c
sample_x86.c	samples: comment out test_i386_invalid_c6c7()	2017-06-14 16:14:36 +07:00
sample_x86_32_gdt_and_seg_regs.c
shellcode.c