mirror of
https://github.com/yuzu-emu/unicorn
synced 2024-11-25 12:28:55 +00:00
120 lines
3.6 KiB
C
120 lines
3.6 KiB
C
/* Unicorn Emulator Engine */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2015 */
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "hw/boards.h"
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#include "hw/sparc/sparc.h"
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#include "sysemu/cpus.h"
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#include "unicorn.h"
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#include "cpu.h"
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#include "unicorn_common.h"
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#include "uc_priv.h"
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const int SPARC64_REGS_STORAGE_SIZE = offsetof(CPUSPARCState, tlb_table);
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static bool sparc_stop_interrupt(int intno)
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{
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switch(intno) {
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default:
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return false;
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case TT_ILL_INSN:
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return true;
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}
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}
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static void sparc_set_pc(struct uc_struct *uc, uint64_t address)
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{
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CPUSPARCState *state = uc->cpu->env_ptr;
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state->pc = address;
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state->npc = address + 4;
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}
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void sparc_reg_reset(struct uc_struct *uc)
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{
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CPUArchState *env = uc->cpu->env_ptr;
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memset(env->gregs, 0, sizeof(env->gregs));
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memset(env->fpr, 0, sizeof(env->fpr));
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memset(env->regbase, 0, sizeof(env->regbase));
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env->pc = 0;
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env->npc = 0;
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env->regwptr = env->regbase;
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}
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int sparc_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals, int count)
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{
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CPUState *mycpu = uc->cpu;
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CPUSPARCState *state = &SPARC_CPU(uc, mycpu)->env;
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int i;
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for (i = 0; i < count; i++) {
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unsigned int regid = regs[i];
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void *value = vals[i];
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if (regid >= UC_SPARC_REG_G0 && regid <= UC_SPARC_REG_G7) {
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*(int64_t *)value = state->gregs[regid - UC_SPARC_REG_G0];
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} else if (regid >= UC_SPARC_REG_O0 && regid <= UC_SPARC_REG_O7) {
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*(int64_t *)value = state->regwptr[regid - UC_SPARC_REG_O0];
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} else if (regid >= UC_SPARC_REG_L0 && regid <= UC_SPARC_REG_L7) {
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*(int64_t *)value = state->regwptr[8 + regid - UC_SPARC_REG_L0];
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} else if (regid >= UC_SPARC_REG_I0 && regid <= UC_SPARC_REG_I7) {
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*(int64_t *)value = state->regwptr[16 + regid - UC_SPARC_REG_I0];
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} else {
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switch(regid) {
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default: break;
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case UC_SPARC_REG_PC:
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*(int64_t *)value = state->pc;
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break;
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}
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}
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}
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return 0;
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}
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int sparc_reg_write(struct uc_struct *uc, unsigned int *regs, void* const* vals, int count)
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{
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CPUState *mycpu = uc->cpu;
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CPUSPARCState *state = &SPARC_CPU(uc, mycpu)->env;
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int i;
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for (i = 0; i < count; i++) {
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unsigned int regid = regs[i];
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const void *value = vals[i];
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if (regid >= UC_SPARC_REG_G0 && regid <= UC_SPARC_REG_G7) {
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state->gregs[regid - UC_SPARC_REG_G0] = *(uint64_t *)value;
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} else if (regid >= UC_SPARC_REG_O0 && regid <= UC_SPARC_REG_O7) {
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state->regwptr[regid - UC_SPARC_REG_O0] = *(uint64_t *)value;
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} else if (regid >= UC_SPARC_REG_L0 && regid <= UC_SPARC_REG_L7) {
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state->regwptr[8 + regid - UC_SPARC_REG_L0] = *(uint64_t *)value;
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} else if (regid >= UC_SPARC_REG_I0 && regid <= UC_SPARC_REG_I7) {
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state->regwptr[16 + regid - UC_SPARC_REG_I0] = *(uint64_t *)value;
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} else {
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switch(regid) {
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default: break;
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case UC_SPARC_REG_PC:
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state->pc = *(uint64_t *)value;
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state->npc = *(uint64_t *)value + 4;
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break;
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}
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}
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}
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return 0;
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}
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DEFAULT_VISIBILITY
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void sparc64_uc_init(struct uc_struct* uc)
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{
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register_accel_types(uc);
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sparc_cpu_register_types(uc);
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sun4u_machine_init(uc);
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uc->reg_read = sparc_reg_read;
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uc->reg_write = sparc_reg_write;
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uc->reg_reset = sparc_reg_reset;
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uc->set_pc = sparc_set_pc;
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uc->stop_interrupt = sparc_stop_interrupt;
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uc_common_init(uc);
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}
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