Eric Blake b239241e99 qapi: Make c_type() more OO-like ... QAPISchemaType.c_type() is a bit awkward: it takes two optional boolean flags is_param and is_unboxed, and they should never both be True. Add a new method for each of the flags, and drop the flags from c_type(). Most callers pass no flags; they remain unchanged. One caller passes is_param=True; call the new .c_param_type() instead. One caller passes is_unboxed=True, except for simple union types. This is actually an ugly special case that will go away soon, so until then, we now have to call either .c_type() or the new .c_unboxed_type(). Tolerable in the interim. It requires slightly more Python, but is arguably easier to read. Backports commit 4040d995e49c5b818be79e50a18c1bf8d2354d12 from qemu		2018-02-21 22:01:09 -05:00
..
crypto
default-configs
docs
fpu	softfloat: Remove lingering fast casts	2018-02-20 19:04:22 -05:00
hw	qom: Allow properties to be registered against classes	2018-02-21 21:00:56 -05:00
include	qapi: Drop QERR_UNKNOWN_BLOCK_FORMAT_FEATURE	2018-02-21 21:55:15 -05:00
qapi	qapi: Don't box branches of flat unions	2018-02-20 16:44:55 -05:00
qobject
qom	qom: Change object property iterator API contract	2018-02-21 21:03:58 -05:00
scripts	qapi: Make c_type() more OO-like	2018-02-21 22:01:09 -05:00
target-arm	target-arm: Fix translation level on early translation faults	2018-02-21 21:53:15 -05:00
target-i386	target-i386: Dump unknown opcodes with -d unimp	2018-02-21 21:37:16 -05:00
target-m68k	tcg: Make store_dummy a TCGv	2018-02-21 00:24:40 -05:00
target-mips	tcg: Make cpu_gpr a TCGv array	2018-02-21 01:02:46 -05:00
target-sparc	tcg: Make cpu_regs_sparc a TCGv array	2018-02-21 01:50:28 -05:00
tcg	tcg: Make cpu_regs_sparc a TCGv array	2018-02-21 01:50:28 -05:00
util	error: ensure errno detail is printed with error_abort	2018-02-21 21:40:24 -05:00
aarch64.h	target-arm: Implement MRS (banked) and MSR (banked) instructions	2018-02-21 21:50:42 -05:00
aarch64eb.h	target-arm: Implement MRS (banked) and MSR (banked) instructions	2018-02-21 21:50:42 -05:00
accel.c
arm.h	target-arm: Implement MRS (banked) and MSR (banked) instructions	2018-02-21 21:50:42 -05:00
armeb.h	target-arm: Implement MRS (banked) and MSR (banked) instructions	2018-02-21 21:50:42 -05:00
CODING_STYLE
configure
COPYING
COPYING.LIB
cpu-exec-common.c
cpu-exec.c
cpus.c
cputlb.c	memory: Drop MemoryRegion.ram_addr	2018-02-21 08:53:08 -05:00
exec.c	exec: fix early return from ram_block_add	2018-02-21 21:37:58 -05:00
gen_all_header.sh
glib_compat.c	glib_compat: backport hashtable iterator interfaces	2018-02-21 13:18:44 -05:00
HACKING
header_gen.py	target-arm: Implement MRS (banked) and MSR (banked) instructions	2018-02-21 21:50:42 -05:00
ioport.c
LICENSE
m68k.h	target-arm: Implement MRS (banked) and MSR (banked) instructions	2018-02-21 21:50:42 -05:00
Makefile
Makefile.objs
Makefile.target
memory.c	qom: Allow properties to be registered against classes	2018-02-21 21:00:56 -05:00
memory_mapping.c
mips.h	target-arm: Implement MRS (banked) and MSR (banked) instructions	2018-02-21 21:50:42 -05:00
mips64.h	target-arm: Implement MRS (banked) and MSR (banked) instructions	2018-02-21 21:50:42 -05:00
mips64el.h	target-arm: Implement MRS (banked) and MSR (banked) instructions	2018-02-21 21:50:42 -05:00
mipsel.h	target-arm: Implement MRS (banked) and MSR (banked) instructions	2018-02-21 21:50:42 -05:00
powerpc.h	target-arm: Implement MRS (banked) and MSR (banked) instructions	2018-02-21 21:50:42 -05:00
qapi-schema.json
qemu-log.c
qemu-timer.c
rules.mak
softmmu_template.h
sparc.h	target-arm: Implement MRS (banked) and MSR (banked) instructions	2018-02-21 21:50:42 -05:00
sparc64.h	target-arm: Implement MRS (banked) and MSR (banked) instructions	2018-02-21 21:50:42 -05:00
tcg-runtime.c
translate-all.c
translate-all.h
translate-common.c
unicorn_common.h
VERSION
vl.c
vl.h
x86_64.h	target-arm: Implement MRS (banked) and MSR (banked) instructions	2018-02-21 21:50:42 -05:00