mirror of
https://github.com/yuzu-emu/unicorn
synced 2024-11-24 23:28:24 +00:00
4fa9ea2ae1
In db432672, we allow wide inputs for operations such as add. However, in 212be173 and 3774030a we didn't do the same for compare and multiply. Backports commit 9a938d86b04025ac605db0ea9819e5896bf576ec from qemu
389 lines
11 KiB
C
389 lines
11 KiB
C
/*
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* Tiny Code Generator for QEMU
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*
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* Copyright (c) 2018 Linaro, Inc.
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu-common.h"
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#include "cpu.h"
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#include "exec/exec-all.h"
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#include "tcg.h"
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#include "tcg-op.h"
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#include "tcg-mo.h"
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/* Reduce the number of ifdefs below. This assumes that all uses of
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TCGV_HIGH and TCGV_LOW are properly protected by a conditional that
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the compiler can eliminate. */
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#if TCG_TARGET_REG_BITS == 64
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extern TCGv_i32 TCGV_LOW_link_error(TCGContext *, TCGv_i64);
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extern TCGv_i32 TCGV_HIGH_link_error(TCGContext *, TCGv_i64);
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#define TCGV_LOW TCGV_LOW_link_error
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#define TCGV_HIGH TCGV_HIGH_link_error
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#endif
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void vec_gen_2(TCGContext *s, TCGOpcode opc, TCGType type, unsigned vece, TCGArg r, TCGArg a)
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{
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TCGOp *op = tcg_emit_op(s, opc);
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TCGOP_VECL(op) = type - TCG_TYPE_V64;
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TCGOP_VECE(op) = vece;
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op->args[0] = r;
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op->args[1] = a;
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}
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void vec_gen_3(TCGContext *s, TCGOpcode opc, TCGType type, unsigned vece,
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TCGArg r, TCGArg a, TCGArg b)
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{
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TCGOp *op = tcg_emit_op(s, opc);
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TCGOP_VECL(op) = type - TCG_TYPE_V64;
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TCGOP_VECE(op) = vece;
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op->args[0] = r;
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op->args[1] = a;
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op->args[2] = b;
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}
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void vec_gen_4(TCGContext *s, TCGOpcode opc, TCGType type, unsigned vece,
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TCGArg r, TCGArg a, TCGArg b, TCGArg c)
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{
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TCGOp *op = tcg_emit_op(s, opc);
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TCGOP_VECL(op) = type - TCG_TYPE_V64;
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TCGOP_VECE(op) = vece;
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op->args[0] = r;
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op->args[1] = a;
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op->args[2] = b;
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op->args[3] = c;
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}
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static void vec_gen_op2(TCGContext *s, TCGOpcode opc, unsigned vece, TCGv_vec r, TCGv_vec a)
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{
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TCGTemp *rt = tcgv_vec_temp(s, r);
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TCGTemp *at = tcgv_vec_temp(s, a);
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TCGType type = rt->base_type;
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/* Must enough inputs for the output. */
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tcg_debug_assert(at->base_type >= type);
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vec_gen_2(s, opc, type, vece, temp_arg(rt), temp_arg(at));
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}
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static void vec_gen_op3(TCGContext *s, TCGOpcode opc, unsigned vece,
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TCGv_vec r, TCGv_vec a, TCGv_vec b)
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{
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TCGTemp *rt = tcgv_vec_temp(s, r);
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TCGTemp *at = tcgv_vec_temp(s, a);
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TCGTemp *bt = tcgv_vec_temp(s, b);
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TCGType type = rt->base_type;
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/* Must enough inputs for the output. */
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tcg_debug_assert(at->base_type >= type);
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tcg_debug_assert(bt->base_type >= type);
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vec_gen_3(s, opc, type, vece, temp_arg(rt), temp_arg(at), temp_arg(bt));
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}
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void tcg_gen_mov_vec(TCGContext *s, TCGv_vec r, TCGv_vec a)
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{
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if (r != a) {
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vec_gen_op2(s, INDEX_op_mov_vec, 0, r, a);
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}
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}
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#define MO_REG (TCG_TARGET_REG_BITS == 64 ? MO_64 : MO_32)
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static void do_dupi_vec(TCGContext *s, TCGv_vec r, unsigned vece, TCGArg a)
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{
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TCGTemp *rt = tcgv_vec_temp(s, r);
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vec_gen_2(s, INDEX_op_dupi_vec, rt->base_type, vece, temp_arg(rt), a);
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}
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TCGv_vec tcg_const_zeros_vec(TCGContext *s, TCGType type)
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{
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TCGv_vec ret = tcg_temp_new_vec(s, type);
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do_dupi_vec(s, ret, MO_REG, 0);
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return ret;
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}
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TCGv_vec tcg_const_ones_vec(TCGContext *s, TCGType type)
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{
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TCGv_vec ret = tcg_temp_new_vec(s, type);
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do_dupi_vec(s, ret, MO_REG, -1);
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return ret;
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}
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TCGv_vec tcg_const_zeros_vec_matching(TCGContext *s, TCGv_vec m)
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{
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TCGTemp *t = tcgv_vec_temp(s, m);
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return tcg_const_zeros_vec(s, t->base_type);
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}
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TCGv_vec tcg_const_ones_vec_matching(TCGContext *s, TCGv_vec m)
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{
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TCGTemp *t = tcgv_vec_temp(s, m);
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return tcg_const_ones_vec(s, t->base_type);
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}
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void tcg_gen_dup64i_vec(TCGContext *s, TCGv_vec r, uint64_t a)
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{
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if (TCG_TARGET_REG_BITS == 32 && a == deposit64(a, 32, 32, a)) {
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do_dupi_vec(s, r, MO_32, a);
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} else if (TCG_TARGET_REG_BITS == 64 || a == (uint64_t)(int32_t)a) {
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do_dupi_vec(s, r, MO_64, a);
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} else {
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TCGv_i64 c = tcg_const_i64(s, a);
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tcg_gen_dup_i64_vec(s, MO_64, r, c);
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tcg_temp_free_i64(s, c);
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}
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}
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void tcg_gen_dup32i_vec(TCGContext *s, TCGv_vec r, uint32_t a)
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{
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do_dupi_vec(s, r, MO_REG, dup_const(MO_32, a));
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}
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void tcg_gen_dup16i_vec(TCGContext *s, TCGv_vec r, uint32_t a)
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{
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do_dupi_vec(s, r, MO_REG, dup_const(MO_16, a));
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}
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void tcg_gen_dup8i_vec(TCGContext *s, TCGv_vec r, uint32_t a)
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{
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do_dupi_vec(s, r, MO_REG, dup_const(MO_8, a));
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}
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void tcg_gen_dupi_vec(TCGContext *s, unsigned vece, TCGv_vec r, uint64_t a)
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{
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do_dupi_vec(s, r, MO_REG, dup_const(vece, a));
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}
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void tcg_gen_dup_i64_vec(TCGContext *s, unsigned vece, TCGv_vec r, TCGv_i64 a)
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{
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TCGArg ri = tcgv_vec_arg(s, r);
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TCGTemp *rt = arg_temp(ri);
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TCGType type = rt->base_type;
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if (TCG_TARGET_REG_BITS == 64) {
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TCGArg ai = tcgv_i64_arg(s, a);
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vec_gen_2(s, INDEX_op_dup_vec, type, vece, ri, ai);
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} else if (vece == MO_64) {
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TCGArg al = tcgv_i32_arg(s, TCGV_LOW(s, a));
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TCGArg ah = tcgv_i32_arg(s, TCGV_HIGH(s, a));
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vec_gen_3(s, INDEX_op_dup2_vec, type, MO_64, ri, al, ah);
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} else {
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TCGArg ai = tcgv_i32_arg(s, TCGV_LOW(s, a));
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vec_gen_2(s, INDEX_op_dup_vec, type, vece, ri, ai);
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}
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}
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void tcg_gen_dup_i32_vec(TCGContext *s, unsigned vece, TCGv_vec r, TCGv_i32 a)
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{
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TCGArg ri = tcgv_vec_arg(s, r);
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TCGArg ai = tcgv_i32_arg(s, a);
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TCGTemp *rt = arg_temp(ri);
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TCGType type = rt->base_type;
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vec_gen_2(s, INDEX_op_dup_vec, type, vece, ri, ai);
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}
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static void vec_gen_ldst(TCGContext *s, TCGOpcode opc, TCGv_vec r, TCGv_ptr b, TCGArg o)
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{
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TCGArg ri = tcgv_vec_arg(s, r);
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TCGArg bi = tcgv_ptr_arg(s, b);
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TCGTemp *rt = arg_temp(ri);
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TCGType type = rt->base_type;
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vec_gen_3(s, opc, type, 0, ri, bi, o);
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}
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void tcg_gen_ld_vec(TCGContext *s, TCGv_vec r, TCGv_ptr b, TCGArg o)
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{
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vec_gen_ldst(s, INDEX_op_ld_vec, r, b, o);
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}
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void tcg_gen_st_vec(TCGContext *s, TCGv_vec r, TCGv_ptr b, TCGArg o)
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{
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vec_gen_ldst(s, INDEX_op_st_vec, r, b, o);
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}
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void tcg_gen_stl_vec(TCGContext *s, TCGv_vec r, TCGv_ptr b, TCGArg o, TCGType low_type)
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{
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TCGArg ri = tcgv_vec_arg(s, r);
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TCGArg bi = tcgv_ptr_arg(s, b);
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TCGTemp *rt = arg_temp(ri);
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TCGType type = rt->base_type;
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tcg_debug_assert(low_type >= TCG_TYPE_V64);
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tcg_debug_assert(low_type <= type);
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vec_gen_3(s, INDEX_op_st_vec, low_type, 0, ri, bi, o);
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}
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void tcg_gen_add_vec(TCGContext *s, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
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{
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vec_gen_op3(s, INDEX_op_add_vec, vece, r, a, b);
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}
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void tcg_gen_sub_vec(TCGContext *s, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
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{
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vec_gen_op3(s, INDEX_op_sub_vec, vece, r, a, b);
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}
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void tcg_gen_and_vec(TCGContext *s, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
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{
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vec_gen_op3(s, INDEX_op_and_vec, 0, r, a, b);
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}
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void tcg_gen_or_vec(TCGContext *s, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
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{
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vec_gen_op3(s, INDEX_op_or_vec, 0, r, a, b);
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}
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void tcg_gen_xor_vec(TCGContext *s, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
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{
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vec_gen_op3(s, INDEX_op_xor_vec, 0, r, a, b);
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}
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void tcg_gen_andc_vec(TCGContext *s, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
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{
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if (TCG_TARGET_HAS_andc_vec) {
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vec_gen_op3(s, INDEX_op_andc_vec, 0, r, a, b);
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} else {
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TCGv_vec t = tcg_temp_new_vec_matching(s, r);
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tcg_gen_not_vec(s, 0, t, b);
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tcg_gen_and_vec(s, 0, r, a, t);
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tcg_temp_free_vec(s, t);
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}
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}
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void tcg_gen_orc_vec(TCGContext *s, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
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{
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if (TCG_TARGET_HAS_orc_vec) {
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vec_gen_op3(s, INDEX_op_orc_vec, 0, r, a, b);
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} else {
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TCGv_vec t = tcg_temp_new_vec_matching(s, r);
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tcg_gen_not_vec(s, 0, t, b);
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tcg_gen_or_vec(s, 0, r, a, t);
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tcg_temp_free_vec(s, t);
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}
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}
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void tcg_gen_not_vec(TCGContext *s, unsigned vece, TCGv_vec r, TCGv_vec a)
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{
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if (TCG_TARGET_HAS_not_vec) {
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vec_gen_op2(s, INDEX_op_not_vec, 0, r, a);
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} else {
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TCGv_vec t = tcg_const_ones_vec_matching(s, r);
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tcg_gen_xor_vec(s, 0, r, a, t);
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tcg_temp_free_vec(s, t);
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}
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}
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void tcg_gen_neg_vec(TCGContext *s, unsigned vece, TCGv_vec r, TCGv_vec a)
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{
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if (TCG_TARGET_HAS_neg_vec) {
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vec_gen_op2(s, INDEX_op_neg_vec, vece, r, a);
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} else {
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TCGv_vec t = tcg_const_zeros_vec_matching(s, r);
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tcg_gen_sub_vec(s, vece, r, t, a);
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tcg_temp_free_vec(s, t);
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}
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}
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static void do_shifti(TCGContext *s, TCGOpcode opc, unsigned vece,
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TCGv_vec r, TCGv_vec a, int64_t i)
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{
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TCGTemp *rt = tcgv_vec_temp(s, r);
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TCGTemp *at = tcgv_vec_temp(s, a);
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TCGArg ri = temp_arg(rt);
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TCGArg ai = temp_arg(at);
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TCGType type = rt->base_type;
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int can;
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tcg_debug_assert(at->base_type == type);
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tcg_debug_assert(i >= 0 && i < (8 << vece));
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if (i == 0) {
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tcg_gen_mov_vec(s, r, a);
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return;
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}
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can = tcg_can_emit_vec_op(opc, type, vece);
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if (can > 0) {
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vec_gen_3(s, opc, type, vece, ri, ai, i);
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} else {
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/* We leave the choice of expansion via scalar or vector shift
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to the target. Often, but not always, dupi can feed a vector
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shift easier than a scalar. */
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tcg_debug_assert(can < 0);
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tcg_expand_vec_op(s, opc, type, vece, ri, ai, i);
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}
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}
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void tcg_gen_shli_vec(TCGContext *s, unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i)
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{
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do_shifti(s, INDEX_op_shli_vec, vece, r, a, i);
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}
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void tcg_gen_shri_vec(TCGContext *s, unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i)
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{
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do_shifti(s, INDEX_op_shri_vec, vece, r, a, i);
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}
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void tcg_gen_sari_vec(TCGContext *s, unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i)
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{
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do_shifti(s, INDEX_op_sari_vec, vece, r, a, i);
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}
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void tcg_gen_cmp_vec(TCGContext *s, TCGCond cond, unsigned vece,
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TCGv_vec r, TCGv_vec a, TCGv_vec b)
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{
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TCGTemp *rt = tcgv_vec_temp(s, r);
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TCGTemp *at = tcgv_vec_temp(s, a);
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TCGTemp *bt = tcgv_vec_temp(s, b);
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TCGArg ri = temp_arg(rt);
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TCGArg ai = temp_arg(at);
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TCGArg bi = temp_arg(bt);
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TCGType type = rt->base_type;
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int can;
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tcg_debug_assert(at->base_type >= type);
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tcg_debug_assert(bt->base_type >= type);
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can = tcg_can_emit_vec_op(INDEX_op_cmp_vec, type, vece);
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if (can > 0) {
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vec_gen_4(s, INDEX_op_cmp_vec, type, vece, ri, ai, bi, cond);
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} else {
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tcg_debug_assert(can < 0);
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tcg_expand_vec_op(s, INDEX_op_cmp_vec, type, vece, ri, ai, bi, cond);
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}
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}
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void tcg_gen_mul_vec(TCGContext *s, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
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{
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TCGTemp *rt = tcgv_vec_temp(s, r);
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TCGTemp *at = tcgv_vec_temp(s, a);
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TCGTemp *bt = tcgv_vec_temp(s, b);
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TCGArg ri = temp_arg(rt);
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TCGArg ai = temp_arg(at);
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TCGArg bi = temp_arg(bt);
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TCGType type = rt->base_type;
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int can;
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tcg_debug_assert(at->base_type >= type);
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tcg_debug_assert(bt->base_type >= type);
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can = tcg_can_emit_vec_op(INDEX_op_mul_vec, type, vece);
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if (can > 0) {
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vec_gen_3(s, INDEX_op_mul_vec, type, vece, ri, ai, bi);
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} else {
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tcg_debug_assert(can < 0);
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tcg_expand_vec_op(s, INDEX_op_mul_vec, type, vece, ri, ai, bi);
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}
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}
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