Peter Maydell c390c07ae0 hw/intc/armv7m_nvic: Implement cache ID registers ... M profile cores have a similar setup for cache ID registers to A profile: * Cache Level ID Register (CLIDR) is a fixed value * Cache Type Register (CTR) is a fixed value * Cache Size ID Registers (CCSIDR) are a bank of registers; which one you see is selected by the Cache Size Selection Register (CSSELR) The only difference is that they're in the NVIC memory mapped register space rather than being coprocessor registers. Implement the M profile view of them. Since neither Cortex-M3 nor Cortex-M4 implement caches, we don't need to update their init functions and can leave the ctr/clidr/ccsidr[] fields in their ARMCPU structs at zero. Newer cores (like the Cortex-M33) will want to be able to set these ID registers to non-zero values, though. Backports commit 43bbce7fbef22adf687dd84934fd0b2f8df807a8 from qemu		2018-03-08 09:35:53 -05:00
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arm	hw/intc/armv7m_nvic: Implement cache ID registers	2018-03-08 09:35:53 -05:00
i386	Include qapi/qmp/qdict.h exactly where needed	2018-03-08 08:51:46 -05:00
m68k	m68k: implement movep instruction	2018-03-07 11:51:32 -05:00
mips	unicorn/mips: Lessen the amount of MIPS_CPU macro usage	2018-03-07 10:50:08 -05:00
sparc	sparc: move adhoc CPUSPARCState initialization to realize time	2018-03-07 21:40:33 -05:00