unicorn/qemu
Peter Maydell c7b5fccfb8
target/arm: Prepare for CONTROL.SPSEL being nonzero in Handler mode
In the v7M architecture, there is an invariant that if the CPU is
in Handler mode then the CONTROL.SPSEL bit cannot be nonzero.
This in turn means that the current stack pointer is always
indicated by CONTROL.SPSEL, even though Handler mode always uses
the Main stack pointer.

In v8M, this invariant is removed, and CONTROL.SPSEL may now
be nonzero in Handler mode (though Handler mode still always
uses the Main stack pointer). In preparation for this change,
change how we handle this bit: rename switch_v7m_sp() to
the now more accurate write_v7m_control_spsel(), and make it
check both the handler mode state and the SPSEL bit.

Note that this implicitly changes the point at which we switch
active SP on exception exit from before we pop the exception
frame to after it.

Backports commit de2db7ec894f11931932ca78cd14a8d2b1389d5b from qemu
2018-03-05 01:29:54 -05:00
..
accel target/arm: [tcg] Port to generic translation framework 2018-03-04 20:28:06 -05:00
crypto
default-configs
docs
fpu
hw mips: replace cpu_mips_init() with cpu_generic_init() 2018-03-05 00:49:10 -05:00
include qom: provide root container for internal objs 2018-03-05 01:16:50 -05:00
qapi
qobject
qom qom: provide root container for internal objs 2018-03-05 01:16:50 -05:00
scripts
target target/arm: Prepare for CONTROL.SPSEL being nonzero in Handler mode 2018-03-05 01:29:54 -05:00
tcg tcg/mips: Fully convert tcg_target_op_def 2018-03-04 23:54:26 -05:00
util bitmap: provide to_le/from_le helpers 2018-03-05 01:11:13 -05:00
aarch64.h target/arm: Prepare for CONTROL.SPSEL being nonzero in Handler mode 2018-03-05 01:29:54 -05:00
aarch64eb.h target/arm: Prepare for CONTROL.SPSEL being nonzero in Handler mode 2018-03-05 01:29:54 -05:00
accel.c
arm.h target/arm: Prepare for CONTROL.SPSEL being nonzero in Handler mode 2018-03-05 01:29:54 -05:00
armeb.h target/arm: Prepare for CONTROL.SPSEL being nonzero in Handler mode 2018-03-05 01:29:54 -05:00
atomic_template.h
CODING_STYLE
configure configure: Drop AIX host support 2018-03-04 21:32:40 -05:00
COPYING
COPYING.LIB
cpu-exec-common.c
cpu-exec.c tcg: Move USE_DIRECT_JUMP discriminator to tcg/cpu/tcg-target.h 2018-03-04 21:52:35 -05:00
cpus.c
cputlb.c cputlb: Support generating CPU exceptions on memory transaction failures 2018-03-04 13:14:50 -05:00
exec.c memory: Open code FlatView rendering 2018-03-04 02:06:48 -05:00
gen_all_header.sh
glib_compat.c
HACKING
header_gen.py target/arm: Prepare for CONTROL.SPSEL being nonzero in Handler mode 2018-03-05 01:29:54 -05:00
ioport.c
LICENSE
m68k.h target/arm: Prepare for CONTROL.SPSEL being nonzero in Handler mode 2018-03-05 01:29:54 -05:00
Makefile
Makefile.objs
Makefile.target tcg: Add generic translation framework 2018-03-04 14:31:16 -05:00
memory.c memory: avoid a name clash with access macro 2018-03-05 01:13:01 -05:00
memory_ldst.inc.c
memory_mapping.c
mips.h target/arm: Prepare for CONTROL.SPSEL being nonzero in Handler mode 2018-03-05 01:29:54 -05:00
mips64.h target/arm: Prepare for CONTROL.SPSEL being nonzero in Handler mode 2018-03-05 01:29:54 -05:00
mips64el.h target/arm: Prepare for CONTROL.SPSEL being nonzero in Handler mode 2018-03-05 01:29:54 -05:00
mipsel.h target/arm: Prepare for CONTROL.SPSEL being nonzero in Handler mode 2018-03-05 01:29:54 -05:00
powerpc.h target/arm: Prepare for CONTROL.SPSEL being nonzero in Handler mode 2018-03-05 01:29:54 -05:00
qapi-schema.json
qemu-timer.c
rules.mak
softmmu_template.h cputlb: Support generating CPU exceptions on memory transaction failures 2018-03-04 13:14:50 -05:00
sparc.h target/arm: Prepare for CONTROL.SPSEL being nonzero in Handler mode 2018-03-05 01:29:54 -05:00
sparc64.h target/arm: Prepare for CONTROL.SPSEL being nonzero in Handler mode 2018-03-05 01:29:54 -05:00
tcg-runtime.c
translate-all.c tcg: Infrastructure for managing constant pools 2018-03-04 22:17:33 -05:00
translate-all.h
translate-common.c
unicorn_common.h
VERSION
vl.c
vl.h
x86_64.h target/arm: Prepare for CONTROL.SPSEL being nonzero in Handler mode 2018-03-05 01:29:54 -05:00