Lioncash b6f752970b target/riscv: Initial introduction of the RISC-V target ... This ports over the RISC-V architecture from Qemu. This is currently a very barebones transition. No code hooking or any fancy stuff. Currently, you can feed it instructions and query the CPU state itself. This also allows choosing whether or not RISC-V 32-bit or RISC-V 64-bit is desirable through Unicorn's interface as well. Extremely basic examples of executing a single instruction have been added to the samples directory to help demonstrate how to use the basic functionality.		2019-03-08 21:46:10 -05:00
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.gitignore
Makefile	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00
mem_apis.c
sample_all.sh
sample_arm.c
sample_arm64.c
sample_arm64eb.c
sample_armeb.c
sample_batch_reg.c
sample_m68k.c
sample_mips.c
sample_riscv.c	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00
sample_sparc.c
sample_x86.c
sample_x86_32_gdt_and_seg_regs.c
shellcode.c