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b3e89e9996
The x86 vector instruction set is extremely irregular. With newer editions, Intel has filled in some of the blanks. However, we don't get many 64-bit operations until SSE4.2, introduced in 2009. The subsequent edition was for AVX1, introduced in 2011, which added three-operand addressing, and adjusts how all instructions should be encoded. Given the relatively narrow 2 year window between possible to support and desirable to support, and to vastly simplify code maintainence, I am only planning to support AVX1 and later cpus. Backports commit 770c2fc7bb70804ae9869995fd02dadd6d7656ac from qemu |
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| tcg-target.h | ||
| tcg-target.inc.c | ||
| tcg-target.opc.h | ||