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Michael Clark d3dbcb6dfc
RISC-V: Add support for vectored interrupts 
If vectored interrupts are enabled (bits[1:0]
of mtvec/stvec == 1) then use the following
logic for trap entry address calculation:

pc = mtvec + cause * 4

In addition to adding support for vectored interrupts
this patch simplifies the interrupt delivery logic
by making sync/async cause decoding and encoding
steps distinct.

The cause code and the sign bit indicating sync/async
is split at the beginning of the function and fixed
cause is renamed to cause. The MSB setting for async
traps is delayed until setting mcause/scause to allow
redundant variables to be eliminated. Some variables
are renamed for conciseness and moved so that decls
are at the start of the block.

Backports commit acbbb94e5730c9808830938e869d243014e2923a from qemu
2019-03-19 23:58:31 -04:00
bindings Added x86Msr functions for the go bindings (#986) 2019-03-08 02:28:37 -05:00
docs fix invalid script path (#975) (#976) 2019-02-28 17:02:06 -05:00
include target/riscv: Initial introduction of the RISC-V target 2019-03-08 21:46:10 -05:00
msvc msvc: Define CONFIG_TCG 2019-01-30 13:52:30 -05:00
qemu RISC-V: Add support for vectored interrupts 2019-03-19 23:58:31 -04:00
samples target/riscv: Initial introduction of the RISC-V target 2019-03-08 21:46:10 -05:00
tests Add missing x86_vec regression test 2019-02-28 17:08:19 -05:00
.appveyor.yml
.gitignore target/riscv: Initial introduction of the RISC-V target 2019-03-08 21:46:10 -05:00
.travis.yml
AUTHORS.TXT
Brewfile
ChangeLog
config.mk
COPYING
COPYING.LGPL2
COPYING_GLIB
CREDITS.TXT Adding Philippe Antoine to CREDITS 2018-10-06 04:50:10 -04:00
install-cmocka-linux.sh
list.c
make.sh
Makefile target/riscv: Initial introduction of the RISC-V target 2019-03-08 21:46:10 -05:00
msvc.bat
pkgconfig.mk
README.md
uc.c target/riscv: Initial introduction of the RISC-V target 2019-03-08 21:46:10 -05:00
windows_export.bat

README.md

Unicorn Engine

Join the chat at https://gitter.im/unicorn-engine/chat

Build Status Build status

Unicorn is a lightweight, multi-platform, multi-architecture CPU emulator framework based on QEMU.

Unicorn offers some unparalleled features:

  • Multi-architecture: ARM, ARM64 (ARMv8), M68K, MIPS, SPARC, and X86 (16, 32, 64-bit)
  • Clean/simple/lightweight/intuitive architecture-neutral API
  • Implemented in pure C language, with bindings for Crystal, Clojure, Visual Basic, Perl, Rust, Ruby, Python, Java, .NET, Go, Delphi/Free Pascal and Haskell.
  • Native support for Windows & *nix (with Mac OSX, Linux, *BSD & Solaris confirmed)
  • High performance via Just-In-Time compilation
  • Support for fine-grained instrumentation at various levels
  • Thread-safety by design
  • Distributed under free software license GPLv2

Further information is available at http://www.unicorn-engine.org

License

This project is released under the GPL license.

Compilation & Docs

See docs/COMPILE.md file for how to compile and install Unicorn.

More documentation is available in docs/README.md.

Contact

Contact us via mailing list, email or twitter for any questions.

Contribute

If you want to contribute, please pick up something from our Github issues.

We also maintain a list of more challenged problems in a TODO list.

CREDITS.TXT records important contributors of our project.