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Eduardo Habkost df51e8bbb3
i386: Disable OSPKE on CPU model definitions 
Currently, the Cascadelake-Server, Icelake-Client, and
Icelake-Server are always generating the following warning:

qemu-system-x86_64: warning: \
host doesn't support requested feature: CPUID.07H:ECX [bit 4]

This happens because OSPKE was never returned by
GET_SUPPORTED_CPUID or x86_cpu_get_supported_feature_word().
OSPKE is a runtime flag automatically set by the KVM module or by
TCG code, was always cleared by x86_cpu_filter_features(), and
was not supposed to appear on the CPU model table.

Remove the OSPKE flag from the CPU model table entries, to avoid
the bogus warning and avoid returning invalid feature data on
query-cpu-* QMP commands. As OSPKE was always cleared by
x86_cpu_filter_features(), this won't have any guest-visible
impact.

Include a test case that should detect the problem if we introduce
a similar bug again.

Fixes: c7a88b52f62b ("i386: Add new model of Cascadelake-Server")
Fixes: 8a11c62da914 ("i386: Add new CPU model Icelake-{Server,Client}")

Backports commit bb4928c7cafe50ab2137a0034e350ef1bfa044d9 from qemu
2019-03-22 09:46:44 -04:00
bindings Added x86Msr functions for the go bindings (#986) 2019-03-08 02:28:37 -05:00
docs fix invalid script path (#975) (#976) 2019-02-28 17:02:06 -05:00
include target/riscv: Initial introduction of the RISC-V target 2019-03-08 21:46:10 -05:00
msvc msvc: Define CONFIG_TCG 2019-01-30 13:52:30 -05:00
qemu i386: Disable OSPKE on CPU model definitions 2019-03-22 09:46:44 -04:00
samples target/riscv: Initial introduction of the RISC-V target 2019-03-08 21:46:10 -05:00
tests Add missing x86_vec regression test 2019-02-28 17:08:19 -05:00
.appveyor.yml
.gitignore target/riscv: Initial introduction of the RISC-V target 2019-03-08 21:46:10 -05:00
.travis.yml use new travis osx image and brew (#935) 2018-01-05 10:29:49 +08:00
AUTHORS.TXT
Brewfile
ChangeLog
config.mk
COPYING
COPYING.LGPL2
COPYING_GLIB
CREDITS.TXT Adding Philippe Antoine to CREDITS 2018-10-06 04:50:10 -04:00
install-cmocka-linux.sh
list.c
make.sh
Makefile target/riscv: Initial introduction of the RISC-V target 2019-03-08 21:46:10 -05:00
msvc.bat
pkgconfig.mk
README.md
uc.c target/riscv: Initial introduction of the RISC-V target 2019-03-08 21:46:10 -05:00
windows_export.bat

README.md

Unicorn Engine

Join the chat at https://gitter.im/unicorn-engine/chat

Build Status Build status

Unicorn is a lightweight, multi-platform, multi-architecture CPU emulator framework based on QEMU.

Unicorn offers some unparalleled features:

  • Multi-architecture: ARM, ARM64 (ARMv8), M68K, MIPS, SPARC, and X86 (16, 32, 64-bit)
  • Clean/simple/lightweight/intuitive architecture-neutral API
  • Implemented in pure C language, with bindings for Crystal, Clojure, Visual Basic, Perl, Rust, Ruby, Python, Java, .NET, Go, Delphi/Free Pascal and Haskell.
  • Native support for Windows & *nix (with Mac OSX, Linux, *BSD & Solaris confirmed)
  • High performance via Just-In-Time compilation
  • Support for fine-grained instrumentation at various levels
  • Thread-safety by design
  • Distributed under free software license GPLv2

Further information is available at http://www.unicorn-engine.org

License

This project is released under the GPL license.

Compilation & Docs

See docs/COMPILE.md file for how to compile and install Unicorn.

More documentation is available in docs/README.md.

Contact

Contact us via mailing list, email or twitter for any questions.

Contribute

If you want to contribute, please pick up something from our Github issues.

We also maintain a list of more challenged problems in a TODO list.

CREDITS.TXT records important contributors of our project.