mirrors-yuzu-emu/yuzu-mainline
1
0
Fork 0
mirror of https://github.com/yuzu-emu/yuzu-mainline synced 2024-11-23 18:43:41 +00:00
Code Issues Projects Releases Packages Wiki Activity

shader_recompiler: Implement LDC.IS address mode

Browse source
This commit is contained in:
Liam 2022-03-16 11:05:04 -04:00
parent 52895fab67
commit 1415542f73
1 changed files with 12 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

14
src/shader_recompiler/frontend/maxwell/translate/impl/load_constant.cpp
View file

@ -11,10 +11,20 @@ namespace Shader::Maxwell {
using namespace LDC; using namespace LDC;
namespace { namespace {
std::pair<IR::U32, IR::U32> Slot(IR::IREmitter& ir, Mode mode, const IR::U32& imm_index, std::pair<IR::U32, IR::U32> Slot(IR::IREmitter& ir, Mode mode, const IR::U32& imm_index,
const IR::U32& reg, const IR::U32& imm) { const IR::U32& reg, const IR::U32& imm_offset) {
switch (mode) { switch (mode) {
case Mode::Default: case Mode::Default:
return {imm_index, ir.IAdd(reg, imm)}; return {imm_index, ir.IAdd(reg, imm_offset)};
case Mode::IS: {
// Segmented addressing mode
// Ra+imm_offset points into a flat mapping of const buffer
// address space
const IR::U32 address{ir.IAdd(reg, imm_offset)};
const IR::U32 index{ir.BitFieldExtract(address, ir.Imm32(16), ir.Imm32(16))};
const IR::U32 offset{ir.BitFieldExtract(address, ir.Imm32(0), ir.Imm32(16))};
return {ir.IAdd(index, imm_index), offset};
}
default: default:
break; break;
} }