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target/mips: Weaken TLB flush on UX,SX,KX,ASID changes

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There is no need to invalidate any shadow TLB entries when the ASID
changes or when access to one of the 64-bit segments has been disabled,
since doing so doesn't reveal to software whether any TLB entries have
been evicted into the shadow half of the TLB.

Therefore weaken the tlb flushes in these cases to only flush the QEMU
TLB.

Backports commit 9658e4c342e6ae0d775101f8f6bb6efb16789af1 from qemu
This commit is contained in:
James Hogan 2018-03-03 23:40:35 -05:00 committed by Lioncash
parent 310e3f0a1d
commit 72677eadd0
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
2 changed files with 2 additions and 2 deletions
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2
qemu/target/mips/helper.c
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@ -278,7 +278,7 @@ void cpu_mips_store_status(CPUMIPSState *env, target_ulong val)
#if defined(TARGET_MIPS64)
if ((env->CP0_Status ^ old) & (old & (7 << CP0St_UX))) {
/* Access to at least one of the 64-bit segments has been disabled */
cpu_mips_tlb_flush(env);
tlb_flush(CPU(mips_env_get_cpu(env)));
}
#endif
if (env->CP0_Config3 & (1 << CP0C3_MT)) {

2
qemu/target/mips/op_helper.c
View file

@ -1410,7 +1410,7 @@ void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1)
/* If the ASID changes, flush qemu's TLB. */
if ((old & env->CP0_EntryHi_ASID_mask) !=
(val & env->CP0_EntryHi_ASID_mask)) {
cpu_mips_tlb_flush(env);
tlb_flush(CPU(mips_env_get_cpu(env)));
}
}