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target/riscv: Remove gen_system()

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with all 16 bit insns moved to decodetree no path is falling back to
gen_system(), so we can remove it.

Backports commit 8f7bc273868939f0821e07fb23792db63d45bffb from qemu
This commit is contained in:
Bastian Koppelmann 2019-03-19 05:36:46 -04:00 committed by Lioncash
parent 1765e6a090
commit a371684da9
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 0 additions and 36 deletions
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36
qemu/target/riscv/translate.c
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@ -492,35 +492,6 @@ static void gen_set_rm(DisasContext *ctx, int rm)
tcg_temp_free_i32(tcg_ctx, t0); tcg_temp_free_i32(tcg_ctx, t0);
} }
static void gen_system(DisasContext *ctx, uint32_t opc, int rd, int rs1,
int csr)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
tcg_gen_movi_tl(tcg_ctx, tcg_ctx->cpu_pc_risc, ctx->base.pc_next);
switch (opc) {
case OPC_RISC_ECALL:
switch (csr) {
case 0x0: /* ECALL */
/* always generates U-level ECALL, fixed in do_interrupt handler */
generate_exception(ctx, RISCV_EXCP_U_ECALL);
tcg_gen_exit_tb(tcg_ctx, NULL, 0); /* no chaining */
ctx->base.is_jmp = DISAS_NORETURN;
break;
case 0x1: /* EBREAK */
generate_exception(ctx, RISCV_EXCP_BREAKPOINT);
tcg_gen_exit_tb(tcg_ctx, NULL, 0); /* no chaining */
ctx->base.is_jmp = DISAS_NORETURN;
break;
default:
gen_exception_illegal(ctx);
break;
}
break;
}
}
static void decode_RV32_64C0(DisasContext *ctx) static void decode_RV32_64C0(DisasContext *ctx)
{ {
uint8_t funct3 = extract32(ctx->opcode, 13, 3); uint8_t funct3 = extract32(ctx->opcode, 13, 3);
@ -704,7 +675,6 @@ bool decode_insn16(DisasContext *ctx, uint16_t insn);
static void decode_RV32_64G(DisasContext *ctx) static void decode_RV32_64G(DisasContext *ctx)
{ {
int rs1, rd;
uint32_t op; uint32_t op;
/* We do not do misaligned address check here: the address should never be /* We do not do misaligned address check here: the address should never be
@ -713,14 +683,8 @@ static void decode_RV32_64G(DisasContext *ctx)
* perform the misaligned instruction fetch */ * perform the misaligned instruction fetch */
op = MASK_OP_MAJOR(ctx->opcode); op = MASK_OP_MAJOR(ctx->opcode);
rs1 = GET_RS1(ctx->opcode);
rd = GET_RD(ctx->opcode);
switch (op) { switch (op) {
case OPC_RISC_SYSTEM:
gen_system(ctx, MASK_OP_SYSTEM(ctx->opcode), rd, rs1,
(ctx->opcode & 0xFFF00000) >> 20);
break;
default: default:
gen_exception_illegal(ctx); gen_exception_illegal(ctx);
break; break;