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target-sparc: Split cpu_put_psr into side-effect and no-side-effect parts
For inbound migration we really want to be able to set the PSR without having any side effects, but cpu_put_psr() calls cpu_check_irqs() which might try to deliver CPU interrupts. Split cpu_put_psr() into the no-side-effect and side-effect parts. This includes reordering the cpu_check_irqs() to the end of cpu_put_psr(), because that function may actually end up calling cpu_interrupt(), which does not seem like a good thing to happen in the middle of updating the PSR. Backports commit 4552a09dd4055c806b7df8c595dc0fb8951834be from qemu
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parent
3dab621825
commit
a734ef8156
5 changed files with 18 additions and 7 deletions
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@ -4179,6 +4179,7 @@ sparc_symbols = (
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'cpu_set_cwp',
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'cpu_get_psr',
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'cpu_put_psr',
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'cpu_put_psr_raw',
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'cpu_cwp_inc',
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'cpu_cwp_dec',
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'helper_save',
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@ -3210,6 +3210,7 @@
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#define cpu_set_cwp cpu_set_cwp_sparc
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#define cpu_get_psr cpu_get_psr_sparc
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#define cpu_put_psr cpu_put_psr_sparc
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#define cpu_put_psr_raw cpu_put_psr_raw_sparc
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#define cpu_cwp_inc cpu_cwp_inc_sparc
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#define cpu_cwp_dec cpu_cwp_dec_sparc
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#define helper_save helper_save_sparc
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@ -3210,6 +3210,7 @@
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#define cpu_set_cwp cpu_set_cwp_sparc64
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#define cpu_get_psr cpu_get_psr_sparc64
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#define cpu_put_psr cpu_put_psr_sparc64
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#define cpu_put_psr_raw cpu_put_psr_raw_sparc64
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#define cpu_cwp_inc cpu_cwp_inc_sparc64
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#define cpu_cwp_dec cpu_cwp_dec_sparc64
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#define helper_save helper_save_sparc64
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@ -542,6 +542,7 @@ int cpu_sparc_exec(struct uc_struct *uc, CPUState *cpu);
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/* win_helper.c */
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target_ulong cpu_get_psr(CPUSPARCState *env1);
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void cpu_put_psr(CPUSPARCState *env1, target_ulong val);
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void cpu_put_psr_raw(CPUSPARCState *env1, target_ulong val);
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#ifdef TARGET_SPARC64
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target_ulong cpu_get_ccr(CPUSPARCState *env1);
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void cpu_put_ccr(CPUSPARCState *env1, target_ulong val);
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@ -63,23 +63,30 @@ target_ulong cpu_get_psr(CPUSPARCState *env)
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#endif
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}
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void cpu_put_psr(CPUSPARCState *env, target_ulong val)
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void cpu_put_psr_raw(CPUSPARCState *env, target_ulong val)
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{
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env->psr = val & PSR_ICC;
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#if !defined(TARGET_SPARC64)
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env->psref = (val & PSR_EF) ? 1 : 0;
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env->psrpil = (val & PSR_PIL) >> 8;
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#endif
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#if ((!defined(TARGET_SPARC64)) && !defined(CONFIG_USER_ONLY))
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//cpu_check_irqs(env);
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#endif
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#if !defined(TARGET_SPARC64)
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env->psrs = (val & PSR_S) ? 1 : 0;
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env->psrps = (val & PSR_PS) ? 1 : 0;
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env->psret = (val & PSR_ET) ? 1 : 0;
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cpu_set_cwp(env, val & PSR_CWP);
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#endif
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env->cc_op = CC_OP_FLAGS;
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#if !defined(TARGET_SPARC64)
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cpu_set_cwp(env, val & PSR_CWP);
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#endif
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}
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void cpu_put_psr(CPUSPARCState *env, target_ulong val)
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{
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cpu_put_psr_raw(env, val);
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#if ((!defined(TARGET_SPARC64)) && !defined(CONFIG_USER_ONLY))
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// Unicorn: commented out
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//cpu_check_irqs(env);
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#endif
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}
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int cpu_cwp_inc(CPUSPARCState *env, int cwp)
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