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RISC-V: Update load reservation comment in do_interrupt

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Backports commit d9360e96885dbd69ce4aa925d1701c7a10cf54ae from qemu
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Michael Clark 2019-03-19 23:53:34 -04:00 committed by Lioncash
parent d3dbcb6dfc
commit b247ee234d
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1 changed files with 7 additions and 1 deletions
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8
qemu/target/riscv/cpu_helper.c
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@ -531,7 +531,13 @@ void riscv_cpu_do_interrupt(CPUState *cs)
((async && (env->mtvec & 3) == 1) ? cause * 4 : 0); ((async && (env->mtvec & 3) == 1) ? cause * 4 : 0);
riscv_cpu_set_mode(env, PRV_M); riscv_cpu_set_mode(env, PRV_M);
} }
/* TODO yield load reservation */
/* NOTE: it is not necessary to yield load reservations here. It is only
* necessary for an SC from "another hart" to cause a load reservation
* to be yielded. Refer to the memory consistency model section of the
* RISC-V ISA Specification.
*/
#endif #endif
cs->exception_index = EXCP_NONE; /* mark handled to qemu */ cs->exception_index = EXCP_NONE; /* mark handled to qemu */
} }