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target-arm: A64: Fix decoding of iss_sf in disas_ld_lit

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Fix the decoding of iss_sf in disas_ld_lit.
The SF (Sixty-Four) field in the ISS (Instruction Specific Syndrome)
is a bit that specifies the width of the register that the
instruction loads to.

If cleared it specifies 32 bits.
If set it specifies 64 bits.

Backports commit 173ff58580b383a7841b18fddb293038c9d40d1c from qemu
This commit is contained in:
Edgar E. Iglesias 2018-02-26 05:01:26 -05:00 committed by Lioncash
parent fa9d708fbd
commit dedab81d68
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 1 additions and 1 deletions
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qemu/target-arm/translate-a64.c
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@ -2067,7 +2067,7 @@ static void disas_ld_lit(DisasContext *s, uint32_t insn)
do_fp_ld(s, rt, tcg_addr, size);
} else {
/* Only unsigned 32bit loads target 32bit registers. */
bool iss_sf = opc == 0 ? 32 : 64;
bool iss_sf = opc != 0;
do_gpr_ld(s, tcg_rt, tcg_addr, size, is_signed, false,
true, rt, iss_sf, false);