Greg Ungerer 1f6f6b2863 m68k: fix usp processing on interrupt entry and exception exit ... The action to potentially switch sp register is not occurring at the correct point in the interrupt entry or exception exit sequences. For the interrupt entry case the sp on entry is used to create the stack exception frame - but this may well be the user stack pointer, since we haven't done the switch yet. Re-order the flow to switch the sp regs then use the current sp to create the exception frame. For the return from exception case the code is unwinding the sp after switching sp registers. But it should always unwind the supervisor sp first, then carry out any required sp switch. Note that these problems don't effect operation unless the user sp bit is set in the CACR register. Only a single sp is used in the default power up state. Previously Linux only used this single sp mode. But modern versions of Linux use the user sp mode now, so we need correct behavior for Linux to work. Backports commit 0c8ff723bd29e5c8b2ca989f857ae5c37ec49c4e from qemu		2018-02-17 15:23:09 -05:00
..
default-configs
docs
fpu
hw
include	softmmu: provide tlb_vaddr_to_host function for user mode	2018-02-17 15:22:43 -05:00
qapi
qobject
qom
scripts
target-arm	target-arm: Add support for Cortex-R5	2018-02-17 15:23:08 -05:00
target-i386	target-i386: create a separate AddressSpace for each CPU	2018-02-13 12:36:26 -05:00
target-m68k	m68k: fix usp processing on interrupt entry and exception exit	2018-02-17 15:23:09 -05:00
target-mips	target-mips: enable XPA and LPA features	2018-02-13 14:14:59 -05:00
target-sparc
tcg
util	bitmap: add atomic test and clear	2018-02-13 10:02:12 -05:00
aarch64.h	target-mips: Misaligned memory accesses for MSA	2018-02-13 13:27:31 -05:00
aarch64eb.h	target-mips: Misaligned memory accesses for MSA	2018-02-13 13:27:31 -05:00
accel.c
arm.h	target-mips: Misaligned memory accesses for MSA	2018-02-13 13:27:31 -05:00
armeb.h	target-mips: Misaligned memory accesses for MSA	2018-02-13 13:27:31 -05:00
CODING_STYLE
configure
COPYING
COPYING.LIB
cpu-exec.c
cpus.c
cputlb.c	memory: replace cpu_physical_memory_reset_dirty() with test-and-clear	2018-02-13 11:25:45 -05:00
exec.c	memory: replace cpu_physical_memory_reset_dirty() with test-and-clear	2018-02-13 11:25:45 -05:00
gen_all_header.sh
glib_compat.c
HACKING
header_gen.py	target-mips: add ERETNC instruction and Config5.LLB bit	2018-02-13 13:33:37 -05:00
ioport.c
LICENSE
m68k.h	target-mips: Misaligned memory accesses for MSA	2018-02-13 13:27:31 -05:00
Makefile
Makefile.objs
Makefile.target
memory.c	memory: use mr->ram_addr in "is this RAM?" assertions	2018-02-13 11:31:02 -05:00
memory_mapping.c
mips.h	target-mips: add ERETNC instruction and Config5.LLB bit	2018-02-13 13:33:37 -05:00
mips64.h	target-mips: add ERETNC instruction and Config5.LLB bit	2018-02-13 13:33:37 -05:00
mips64el.h	target-mips: add ERETNC instruction and Config5.LLB bit	2018-02-13 13:33:37 -05:00
mipsel.h	target-mips: add ERETNC instruction and Config5.LLB bit	2018-02-13 13:33:37 -05:00
powerpc.h	target-mips: Misaligned memory accesses for MSA	2018-02-13 13:27:31 -05:00
qapi-schema.json
qemu-log.c
qemu-timer.c
rules.mak
softmmu_template.h
sparc.h	target-mips: Misaligned memory accesses for MSA	2018-02-13 13:27:31 -05:00
sparc64.h	target-mips: Misaligned memory accesses for MSA	2018-02-13 13:27:31 -05:00
tcg-runtime.c
translate-all.c	translate-all: fix watchpoints if retranslation not possible	2018-02-17 15:22:43 -05:00
translate-all.h	translate-all: remove unnecessary argument to tb_invalidate_phys_range	2018-02-13 09:04:51 -05:00
unicorn_common.h
VERSION
vl.c
vl.h
x86_64.h	target-mips: Misaligned memory accesses for MSA	2018-02-13 13:27:31 -05:00