unicorn/qemu/target-m68k
Greg Ungerer 1f6f6b2863
m68k: fix usp processing on interrupt entry and exception exit
The action to potentially switch sp register is not occurring at the correct
point in the interrupt entry or exception exit sequences.

For the interrupt entry case the sp on entry is used to create the stack
exception frame - but this may well be the user stack pointer, since we
haven't done the switch yet. Re-order the flow to switch the sp regs then
use the current sp to create the exception frame.

For the return from exception case the code is unwinding the sp after
switching sp registers. But it should always unwind the supervisor sp
first, then carry out any required sp switch.

Note that these problems don't effect operation unless the user sp bit is
set in the CACR register. Only a single sp is used in the default power up
state. Previously Linux only used this single sp mode. But modern versions
of Linux use the user sp mode now, so we need correct behavior for Linux
to work.

Backports commit 0c8ff723bd29e5c8b2ca989f857ae5c37ec49c4e from qemu
2018-02-17 15:23:09 -05:00
..
cpu-qom.h remove slow cpu QOM casts (#815) 2017-05-02 14:56:39 +08:00
cpu.c M68K support added. (#735) 2017-01-23 14:40:02 +08:00
cpu.h
helper.c
helper.h rework code/block tracing 2016-01-22 18:42:27 -08:00
m68k-qreg.h
Makefile.objs del qemu/target-m68k/m68k-semi.c 2017-01-20 11:52:31 +08:00
op_helper.c m68k: fix usp processing on interrupt entry and exception exit 2018-02-17 15:23:09 -05:00
qregs.def
translate.c m68k: implement move to/from usp register instruction 2018-02-17 15:23:09 -05:00
unicorn.c M68K support added. (#735) 2017-01-23 14:40:02 +08:00
unicorn.h New feature: registers can be bulk saved/restored in an opaque blob 2016-08-20 04:14:07 -07:00