mirror of
https://github.com/yuzu-emu/unicorn
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7d933a6ba9
Define the MPUIR register for MPU supporting ARMv6 and onwards. Currently we only support unified MPU. The size of the unified MPU is defined via the number of "dregions". So just a single config is added to specify this size. (When split MPU is implemented we will add an extra iregions config). Backports commit 3281af8114c6b8ead02f08b58e3c36895c1ea047 from qemu
231 lines
6.8 KiB
C
231 lines
6.8 KiB
C
/*
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* QEMU ARM CPU
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*
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* Copyright (c) 2012 SUSE LINUX Products GmbH
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see
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* <http://www.gnu.org/licenses/gpl-2.0.html>
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*/
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#ifndef QEMU_ARM_CPU_QOM_H
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#define QEMU_ARM_CPU_QOM_H
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#include "qom/cpu.h"
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#define TYPE_ARM_CPU "arm-cpu"
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#define ARM_CPU_CLASS(uc, klass) \
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OBJECT_CLASS_CHECK(uc, ARMCPUClass, (klass), TYPE_ARM_CPU)
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#define ARM_CPU(uc, obj) ((ARMCPU *)obj)
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#define ARM_CPU_GET_CLASS(uc, obj) \
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OBJECT_GET_CLASS(uc, ARMCPUClass, (obj), TYPE_ARM_CPU)
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/**
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* ARMCPUClass:
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* @parent_realize: The parent class' realize handler.
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* @parent_reset: The parent class' reset handler.
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*
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* An ARM CPU model.
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*/
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typedef struct ARMCPUClass {
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/*< private >*/
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CPUClass parent_class;
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/*< public >*/
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DeviceRealize parent_realize;
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void (*parent_reset)(CPUState *cpu);
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} ARMCPUClass;
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/**
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* ARMCPU:
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* @env: #CPUARMState
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*
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* An ARM CPU core.
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*/
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typedef struct ARMCPU {
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/*< private >*/
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CPUState parent_obj;
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/*< public >*/
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CPUARMState env;
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/* Coprocessor information */
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GHashTable *cp_regs;
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/* For marshalling (mostly coprocessor) register state between the
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* kernel and QEMU (for KVM) and between two QEMUs (for migration),
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* we use these arrays.
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*/
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/* List of register indexes managed via these arrays; (full KVM style
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* 64 bit indexes, not CPRegInfo 32 bit indexes)
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*/
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uint64_t *cpreg_indexes;
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/* Values of the registers (cpreg_indexes[i]'s value is cpreg_values[i]) */
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uint64_t *cpreg_values;
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/* Length of the indexes, values, reset_values arrays */
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int32_t cpreg_array_len;
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/* These are used only for migration: incoming data arrives in
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* these fields and is sanity checked in post_load before copying
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* to the working data structures above.
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*/
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uint64_t *cpreg_vmstate_indexes;
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uint64_t *cpreg_vmstate_values;
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int32_t cpreg_vmstate_array_len;
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/* Timers used by the generic (architected) timer */
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//QEMUTimer *gt_timer[NUM_GTIMERS];
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/* GPIO outputs for generic timer */
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//qemu_irq gt_timer_outputs[NUM_GTIMERS];
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/* 'compatible' string for this CPU for Linux device trees */
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const char *dtb_compatible;
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/* PSCI version for this CPU
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* Bits[31:16] = Major Version
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* Bits[15:0] = Minor Version
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*/
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uint32_t psci_version;
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/* Should CPU start in PSCI powered-off state? */
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bool start_powered_off;
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/* CPU currently in PSCI powered-off state */
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bool powered_off;
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/* CPU has security extension */
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bool has_el3;
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/* CPU has memory protection unit */
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bool has_mpu;
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/* PMSAv7 MPU number of supported regions */
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uint32_t pmsav7_dregion;
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/* PSCI conduit used to invoke PSCI methods
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* 0 - disabled, 1 - smc, 2 - hvc
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*/
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uint32_t psci_conduit;
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/* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or
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* QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type.
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*/
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uint32_t kvm_target;
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/* KVM init features for this CPU */
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uint32_t kvm_init_features[7];
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/* Uniprocessor system with MP extensions */
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bool mp_is_up;
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/* The instance init functions for implementation-specific subclasses
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* set these fields to specify the implementation-dependent values of
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* various constant registers and reset values of non-constant
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* registers.
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* Some of these might become QOM properties eventually.
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* Field names match the official register names as defined in the
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* ARMv7AR ARM Architecture Reference Manual. A reset_ prefix
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* is used for reset values of non-constant registers; no reset_
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* prefix means a constant register.
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*/
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uint32_t midr;
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uint32_t revidr;
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uint32_t reset_fpsid;
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uint32_t mvfr0;
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uint32_t mvfr1;
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uint32_t mvfr2;
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uint32_t ctr;
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uint32_t reset_sctlr;
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uint32_t id_pfr0;
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uint32_t id_pfr1;
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uint32_t id_dfr0;
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uint32_t id_afr0;
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uint32_t id_mmfr0;
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uint32_t id_mmfr1;
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uint32_t id_mmfr2;
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uint32_t id_mmfr3;
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uint32_t id_isar0;
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uint32_t id_isar1;
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uint32_t id_isar2;
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uint32_t id_isar3;
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uint32_t id_isar4;
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uint32_t id_isar5;
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uint64_t id_aa64pfr0;
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uint64_t id_aa64pfr1;
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uint64_t id_aa64dfr0;
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uint64_t id_aa64dfr1;
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uint64_t id_aa64afr0;
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uint64_t id_aa64afr1;
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uint64_t id_aa64isar0;
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uint64_t id_aa64isar1;
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uint64_t id_aa64mmfr0;
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uint64_t id_aa64mmfr1;
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uint32_t dbgdidr;
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uint32_t clidr;
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uint64_t mp_affinity; /* MP ID without feature bits */
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/* The elements of this array are the CCSIDR values for each cache,
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* in the order L1DCache, L1ICache, L2DCache, L2ICache, etc.
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*/
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uint32_t ccsidr[16];
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uint64_t reset_cbar;
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uint32_t reset_auxcr;
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bool reset_hivecs;
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/* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */
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uint32_t dcz_blocksize;
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uint64_t rvbar;
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} ARMCPU;
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#define TYPE_AARCH64_CPU "aarch64-cpu"
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#define AARCH64_CPU_CLASS(klass) \
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OBJECT_CLASS_CHECK(AArch64CPUClass, (klass), TYPE_AARCH64_CPU)
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#define AARCH64_CPU_GET_CLASS(obj) \
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OBJECT_GET_CLASS(AArch64CPUClass, (obj), TYPE_AArch64_CPU)
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typedef struct AArch64CPUClass {
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/*< private >*/
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ARMCPUClass parent_class;
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/*< public >*/
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} AArch64CPUClass;
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static inline ARMCPU *arm_env_get_cpu(CPUARMState *env)
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{
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return container_of(env, ARMCPU, env);
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}
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#define ENV_GET_CPU(e) CPU(arm_env_get_cpu(e))
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#define ENV_OFFSET offsetof(ARMCPU, env)
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#ifndef CONFIG_USER_ONLY
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extern const struct VMStateDescription vmstate_arm_cpu;
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#endif
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void register_cp_regs_for_features(ARMCPU *cpu);
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void init_cpreg_list(ARMCPU *cpu);
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void arm_cpu_do_interrupt(CPUState *cpu);
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void arm_v7m_cpu_do_interrupt(CPUState *cpu);
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bool arm_cpu_exec_interrupt(CPUState *cpu, int int_req);
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hwaddr arm_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
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int arm_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
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int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
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/* Callback functions for the generic timer's timers. */
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void arm_gt_ptimer_cb(void *opaque);
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void arm_gt_vtimer_cb(void *opaque);
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#ifdef TARGET_AARCH64
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int aarch64_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
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int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
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void aarch64_cpu_do_interrupt(CPUState *cs);
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#endif
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#endif
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