mirror of
https://github.com/yuzu-emu/unicorn
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59865351e0
CP0.PageGrain.ELPA enables support for large physical addresses. This field is encoded as follows: 0: Large physical address support is disabled. 1: Large physical address support is enabled. If this bit is a 1, the following changes occur to coprocessor 0 registers: - The PFNX field of the EntryLo0 and EntryLo1 registers is writable and concatenated with the PFN field to form the full page frame number. - Access to optional COP0 registers with PA extension, LLAddr, TagLo is defined. P5600 can operate in 32-bit or 40-bit Physical Address Mode. Therefore if XPA is disabled (CP0.PageGrain.ELPA = 0) then assume 32-bit Address Mode. In MIPS64 assume 36 as default PABITS (when CP0.PageGrain.ELPA = 0). env->PABITS value is constant and indicates maximum PABITS available on a core, whereas env->PAMask is calculated from env->PABITS and is also affected by CP0.PageGrain.ELPA. Backports commit e117f52636d04502fab28bd3abe93347c29f39a5 from qemu
91 lines
2.9 KiB
C
91 lines
2.9 KiB
C
#if !defined (__QEMU_MIPS_DEFS_H__)
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#define __QEMU_MIPS_DEFS_H__
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/* If we want to use host float regs... */
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//#define USE_HOST_FLOAT_REGS
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/* Real pages are variable size... */
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#define TARGET_PAGE_BITS 12
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#define MIPS_TLB_MAX 128
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#if defined(TARGET_MIPS64)
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#define TARGET_LONG_BITS 64
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#define TARGET_PHYS_ADDR_SPACE_BITS 48
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#define TARGET_VIRT_ADDR_SPACE_BITS 42
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#else
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#define TARGET_LONG_BITS 32
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#define TARGET_PHYS_ADDR_SPACE_BITS 40
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#define TARGET_VIRT_ADDR_SPACE_BITS 32
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#endif
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/* Masks used to mark instructions to indicate which ISA level they
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were introduced in. */
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#define ISA_MIPS1 0x00000001
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#define ISA_MIPS2 0x00000002
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#define ISA_MIPS3 0x00000004
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#define ISA_MIPS4 0x00000008
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#define ISA_MIPS5 0x00000010
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#define ISA_MIPS32 0x00000020
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#define ISA_MIPS32R2 0x00000040
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#define ISA_MIPS64 0x00000080
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#define ISA_MIPS64R2 0x00000100
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#define ISA_MIPS32R3 0x00000200
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#define ISA_MIPS64R3 0x00000400
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#define ISA_MIPS32R5 0x00000800
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#define ISA_MIPS64R5 0x00001000
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#define ISA_MIPS32R6 0x00002000
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#define ISA_MIPS64R6 0x00004000
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/* MIPS ASEs. */
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#define ASE_MIPS16 0x00010000
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#define ASE_MIPS3D 0x00020000
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#define ASE_MDMX 0x00040000
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#define ASE_DSP 0x00080000
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#define ASE_DSPR2 0x00100000
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#define ASE_MT 0x00200000
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#define ASE_SMARTMIPS 0x00400000
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#define ASE_MICROMIPS 0x00800000
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#define ASE_MSA 0x01000000
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/* Chip specific instructions. */
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#define INSN_LOONGSON2E 0x20000000
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#define INSN_LOONGSON2F 0x40000000
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#define INSN_VR54XX 0x80000000
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/* MIPS CPU defines. */
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#define CPU_MIPS1 (ISA_MIPS1)
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#define CPU_MIPS2 (CPU_MIPS1 | ISA_MIPS2)
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#define CPU_MIPS3 (CPU_MIPS2 | ISA_MIPS3)
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#define CPU_MIPS4 (CPU_MIPS3 | ISA_MIPS4)
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#define CPU_VR54XX (CPU_MIPS4 | INSN_VR54XX)
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#define CPU_LOONGSON2E (CPU_MIPS3 | INSN_LOONGSON2E)
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#define CPU_LOONGSON2F (CPU_MIPS3 | INSN_LOONGSON2F)
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#define CPU_MIPS5 (CPU_MIPS4 | ISA_MIPS5)
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/* MIPS Technologies "Release 1" */
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#define CPU_MIPS32 (CPU_MIPS2 | ISA_MIPS32)
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#define CPU_MIPS64 (CPU_MIPS5 | CPU_MIPS32 | ISA_MIPS64)
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/* MIPS Technologies "Release 2" */
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#define CPU_MIPS32R2 (CPU_MIPS32 | ISA_MIPS32R2)
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#define CPU_MIPS64R2 (CPU_MIPS64 | CPU_MIPS32R2 | ISA_MIPS64R2)
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/* MIPS Technologies "Release 3" */
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#define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS32R3)
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#define CPU_MIPS64R3 (CPU_MIPS64R2 | CPU_MIPS32R3 | ISA_MIPS64R3)
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/* MIPS Technologies "Release 5" */
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#define CPU_MIPS32R5 (CPU_MIPS32R3 | ISA_MIPS32R5)
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#define CPU_MIPS64R5 (CPU_MIPS64R3 | CPU_MIPS32R5 | ISA_MIPS64R5)
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/* MIPS Technologies "Release 6" */
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#define CPU_MIPS32R6 (CPU_MIPS32R5 | ISA_MIPS32R6)
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#define CPU_MIPS64R6 (CPU_MIPS64R5 | CPU_MIPS32R6 | ISA_MIPS64R6)
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/* Strictly follow the architecture standard:
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- Disallow "special" instruction handling for PMON/SPIM.
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Note that we still maintain Count/Compare to match the host clock. */
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//#define MIPS_STRICT_STANDARD 1
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#endif /* !defined (__QEMU_MIPS_DEFS_H__) */
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