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Dongjiu Geng 4dc3d59fd3
target/arm: change arch timer registers access permission 
Some generic arch timer registers are Config-RW in the EL0,
which means the EL0 exception level can have write permission
if it is appropriately configured.

When VM access registers, QEMU firstly checks whether they have RW
permission, then check whether it is appropriately configured.
If they are defined to read only in EL0, even though they have been
appropriately configured, they still do not have write permission.
So need to add the write permission according to ARMV8 spec when
define it.

Backports commit daf1dc5f82cefe2a57f184d5053e8b274ad2ba9a from qemu
2019-03-19 05:40:44 -04:00
bindings Added x86Msr functions for the go bindings (#986) 2019-03-08 02:28:37 -05:00
docs fix invalid script path (#975) (#976) 2019-02-28 17:02:06 -05:00
include target/riscv: Initial introduction of the RISC-V target 2019-03-08 21:46:10 -05:00
msvc msvc: Define CONFIG_TCG 2019-01-30 13:52:30 -05:00
qemu target/arm: change arch timer registers access permission 2019-03-19 05:40:44 -04:00
samples target/riscv: Initial introduction of the RISC-V target 2019-03-08 21:46:10 -05:00
tests Add missing x86_vec regression test 2019-02-28 17:08:19 -05:00
.appveyor.yml MSYS test (#852) 2017-06-25 10:11:35 +08:00
.gitignore target/riscv: Initial introduction of the RISC-V target 2019-03-08 21:46:10 -05:00
.travis.yml use new travis osx image and brew (#935) 2018-01-05 10:29:49 +08:00
AUTHORS.TXT
Brewfile Update Brewfile 2017-09-30 17:36:44 +07:00
ChangeLog
config.mk
COPYING
COPYING.LGPL2 LGPL2 for all header files under include/unicorn/ 2017-12-16 10:08:42 +08:00
COPYING_GLIB
CREDITS.TXT Adding Philippe Antoine to CREDITS 2018-10-06 04:50:10 -04:00
install-cmocka-linux.sh Start moving examples in S files (#851) 2017-06-25 10:14:22 +08:00
list.c callback to count number of instructions in uc_emu_start() should be executed first. fix #727 2017-06-16 13:22:38 +08:00
make.sh
Makefile target/riscv: Initial introduction of the RISC-V target 2019-03-08 21:46:10 -05:00
msvc.bat
pkgconfig.mk
README.md add Clojure 2017-12-23 00:32:33 +08:00
uc.c target/riscv: Initial introduction of the RISC-V target 2019-03-08 21:46:10 -05:00
windows_export.bat

README.md

Unicorn Engine

Join the chat at https://gitter.im/unicorn-engine/chat

Build Status Build status

Unicorn is a lightweight, multi-platform, multi-architecture CPU emulator framework based on QEMU.

Unicorn offers some unparalleled features:

  • Multi-architecture: ARM, ARM64 (ARMv8), M68K, MIPS, SPARC, and X86 (16, 32, 64-bit)
  • Clean/simple/lightweight/intuitive architecture-neutral API
  • Implemented in pure C language, with bindings for Crystal, Clojure, Visual Basic, Perl, Rust, Ruby, Python, Java, .NET, Go, Delphi/Free Pascal and Haskell.
  • Native support for Windows & *nix (with Mac OSX, Linux, *BSD & Solaris confirmed)
  • High performance via Just-In-Time compilation
  • Support for fine-grained instrumentation at various levels
  • Thread-safety by design
  • Distributed under free software license GPLv2

Further information is available at http://www.unicorn-engine.org

License

This project is released under the GPL license.

Compilation & Docs

See docs/COMPILE.md file for how to compile and install Unicorn.

More documentation is available in docs/README.md.

Contact

Contact us via mailing list, email or twitter for any questions.

Contribute

If you want to contribute, please pick up something from our Github issues.

We also maintain a list of more challenged problems in a TODO list.

CREDITS.TXT records important contributors of our project.