Dongjiu Geng 4dc3d59fd3 target/arm: change arch timer registers access permission ... Some generic arch timer registers are Config-RW in the EL0, which means the EL0 exception level can have write permission if it is appropriately configured. When VM access registers, QEMU firstly checks whether they have RW permission, then check whether it is appropriately configured. If they are defined to read only in EL0, even though they have been appropriately configured, they still do not have write permission. So need to add the write permission according to ARMV8 spec when define it. Backports commit daf1dc5f82cefe2a57f184d5053e8b274ad2ba9a from qemu		2019-03-19 05:40:44 -04:00
..
accel	cputlb: update TLB entry/index after tlb_fill	2019-02-12 11:48:48 -05:00
crypto
default-configs	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00
docs
fpu	qemu/fpu: Synchronize with Qemu	2019-03-09 18:27:31 -05:00
hw	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00
include	qemu/fpu: Synchronize with Qemu	2019-03-09 18:27:31 -05:00
qapi
qobject
qom	qom/cpu: Add cluster_index to CPUState	2019-01-30 12:59:59 -05:00
scripts	decodetree: Properly diagnose fields overflowing an insn	2019-03-13 11:21:04 -04:00
target	target/arm: change arch timer registers access permission	2019-03-19 05:40:44 -04:00
tcg	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00
util	mmap-alloc: fix hugetlbfs misaligned length in ppc64	2019-02-05 16:52:39 -05:00
aarch64.h	qemu/fpu: Synchronize with Qemu	2019-03-09 18:27:31 -05:00
aarch64eb.h	qemu/fpu: Synchronize with Qemu	2019-03-09 18:27:31 -05:00
accel.c
arm.h	qemu/fpu: Synchronize with Qemu	2019-03-09 18:27:31 -05:00
armeb.h	qemu/fpu: Synchronize with Qemu	2019-03-09 18:27:31 -05:00
CODING_STYLE
configure	configure: Disable W^X on OpenBSD	2019-03-11 16:46:52 -04:00
COPYING
COPYING.LIB
cpus.c
exec.c	exec.c: refactor function flatview_add_to_dispatch()	2019-03-11 17:00:46 -04:00
gen_all_header.sh
glib_compat.c	target/arm: expose remaining CPUID registers as RAZ	2019-02-15 17:48:37 -05:00
HACKING
header_gen.py	target/riscv: Convert quadrant 0 of RVXC insns to decodetree	2019-03-19 04:45:53 -04:00
ioport.c
LICENSE
m68k.h	qemu/fpu: Synchronize with Qemu	2019-03-09 18:27:31 -05:00
Makefile
Makefile.objs
Makefile.target
memory.c
memory_ldst.inc.c
memory_mapping.c
mips.h	qemu/fpu: Synchronize with Qemu	2019-03-09 18:27:31 -05:00
mips64.h	qemu/fpu: Synchronize with Qemu	2019-03-09 18:27:31 -05:00
mips64el.h	qemu/fpu: Synchronize with Qemu	2019-03-09 18:27:31 -05:00
mipsel.h	qemu/fpu: Synchronize with Qemu	2019-03-09 18:27:31 -05:00
powerpc.h	qemu/fpu: Synchronize with Qemu	2019-03-09 18:27:31 -05:00
qemu-timer.c
riscv32.h	target/riscv: Convert quadrant 0 of RVXC insns to decodetree	2019-03-19 04:45:53 -04:00
riscv64.h	target/riscv: Convert quadrant 0 of RVXC insns to decodetree	2019-03-19 04:45:53 -04:00
rules.mak
sparc.h	qemu/fpu: Synchronize with Qemu	2019-03-09 18:27:31 -05:00
sparc64.h	qemu/fpu: Synchronize with Qemu	2019-03-09 18:27:31 -05:00
unicorn_common.h
VERSION
vl.c
vl.h
x86_64.h	qemu/fpu: Synchronize with Qemu	2019-03-09 18:27:31 -05:00