Peter Maydell 8e7ecd89a4 target/arm/translate.c: Fix missing 'break' for TT insns ... The code where we added the TT instruction was accidentally missing a 'break', which meant that after generating the code to execute the TT we would fall through to 'goto illegal_op' and generate code to take an UNDEF insn. Backports commit 384c6c03fb687bea239a5990a538c4bc50fdcecb from qemu		2018-03-07 11:45:39 -05:00
..
arm-powerctl.c
arm-powerctl.h
arm_ldst.h
cpu-qom.h
cpu.c	nvic: Implement AIRCR changes for v8M	2018-03-07 08:30:34 -05:00
cpu.h	target/arm: Add SVE state to TB->FLAGS	2018-03-07 11:44:32 -05:00
cpu64.c	target/arm: enable user-mode SHA-3, SM3, SM4 and SHA-512 instruction support	2018-03-07 08:58:43 -05:00
crypto_helper.c	target/arm: implement SM4 instructions	2018-03-07 08:57:53 -05:00
helper-a64.c	target/arm: Fix stlxp for aarch64_be	2018-03-06 08:48:12 -05:00
helper-a64.h
helper.c	target/arm: Add SVE state to TB->FLAGS	2018-03-07 11:44:32 -05:00
helper.h	target/arm: implement SM4 instructions	2018-03-07 08:57:53 -05:00
internals.h	target/arm: Handle page table walk load failures correctly	2018-03-06 08:55:08 -05:00
iwmmxt_helper.c
kvm-consts.h
Makefile.objs
neon_helper.c	target/arm: Use pointers in neon zip/uzp helpers	2018-03-06 10:17:51 -05:00
op_addsub.h
op_helper.c	accel/tcg: add size paremeter in tlb_fill()	2018-03-06 10:56:34 -05:00
psci.c
translate-a64.c	target/arm: Add SVE state to TB->FLAGS	2018-03-07 11:44:32 -05:00
translate.c	target/arm/translate.c: Fix missing 'break' for TT insns	2018-03-07 11:45:39 -05:00
translate.h	target/arm: Add SVE state to TB->FLAGS	2018-03-07 11:44:32 -05:00
unicorn.h
unicorn_aarch64.c	unicorn/aarch64: Use qemu-provided helpers for accessing VFP/NEON/SIMD registers	2018-03-07 11:25:41 -05:00
unicorn_arm.c	unicorn/aarch64: Use qemu-provided helpers for accessing VFP/NEON/SIMD registers	2018-03-07 11:25:41 -05:00