Dongjiu Geng 4dc3d59fd3 target/arm: change arch timer registers access permission ... Some generic arch timer registers are Config-RW in the EL0, which means the EL0 exception level can have write permission if it is appropriately configured. When VM access registers, QEMU firstly checks whether they have RW permission, then check whether it is appropriately configured. If they are defined to read only in EL0, even though they have been appropriately configured, they still do not have write permission. So need to add the write permission according to ARMV8 spec when define it. Backports commit daf1dc5f82cefe2a57f184d5053e8b274ad2ba9a from qemu		2019-03-19 05:40:44 -04:00
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arm	target/arm: change arch timer registers access permission	2019-03-19 05:40:44 -04:00
i386	i386: extended the cpuid_level when Intel PT is enabled	2019-03-11 16:40:23 -04:00
m68k
mips	target/mips: Restore Qemu's organization of CPU definitions	2019-03-08 01:40:50 -05:00
riscv	target/riscv: Remove decode_RV32_64G()	2019-03-19 05:37:42 -04:00
sparc