Alex Bennée d5f002b39a arm/translate-a64: add FP16 FPRINTx to simd_two_reg_misc_fp16 ... This adds the full range of half-precision floating point to integral instructions. Backports commit 6109aea2d954891027acba64a13f1f1c7463cfac from qemu		2018-03-08 18:21:58 -05:00
..
arm-powerctl.c
arm-powerctl.h
arm_ldst.h
cpu-qom.h
cpu.c	target/*/cpu.h: remove softfloat.h	2018-03-08 09:58:47 -05:00
cpu.h	target/arm/cpu.h: add additional float_status flags	2018-03-08 12:34:39 -05:00
cpu64.c	target/arm: enable user-mode SHA-3, SM3, SM4 and SHA-512 instruction support	2018-03-07 08:58:43 -05:00
crypto_helper.c	target/arm: implement SM4 instructions	2018-03-07 08:57:53 -05:00
helper-a64.c	arm/translate-a64: add FP16 FPRINTx to simd_two_reg_misc_fp16	2018-03-08 18:21:58 -05:00
helper-a64.h	arm/translate-a64: add FP16 FPRINTx to simd_two_reg_misc_fp16	2018-03-08 18:21:58 -05:00
helper.c	target/arm/helper: pass explicit fpst to set_rmode	2018-03-08 12:41:54 -05:00
helper.h	target/arm/helper: pass explicit fpst to set_rmode	2018-03-08 12:41:54 -05:00
internals.h	target/arm: Enforce access to ZCR_EL at translation	2018-03-08 09:17:33 -05:00
iwmmxt_helper.c
kvm-consts.h
Makefile.objs
neon_helper.c	target/*/cpu.h: remove softfloat.h	2018-03-08 09:58:47 -05:00
op_addsub.h
op_helper.c
psci.c
translate-a64.c	arm/translate-a64: add FP16 FPRINTx to simd_two_reg_misc_fp16	2018-03-08 18:21:58 -05:00
translate.c	target/arm/helper: pass explicit fpst to set_rmode	2018-03-08 12:41:54 -05:00
translate.h	target/arm: Add SVE state to TB->FLAGS	2018-03-07 11:44:32 -05:00
unicorn.h
unicorn_aarch64.c	unicorn/aarch64: Use qemu-provided helpers for accessing VFP/NEON/SIMD registers	2018-03-07 11:25:41 -05:00
unicorn_arm.c	unicorn/aarch64: Use qemu-provided helpers for accessing VFP/NEON/SIMD registers	2018-03-07 11:25:41 -05:00