Peter Maydell 5812f7e3a3 target/arm: Implement writing to CONTROL_NS for v8M ... In commit 50f11062d4c896 we added support for MSR/MRS access to the NS banked special registers, but we forgot to implement the support for writing to CONTROL_NS. Correct the omission. Backports commit 6eb3a64e2a96f5ced1f7896042b01f002bf0a91f from qemu		2018-03-08 09:39:43 -05:00
..
arm-powerctl.c
arm-powerctl.h
arm_ldst.h
cpu-qom.h
cpu.c	hw/intc/armv7m_nvic: Don't hardcode M profile ID registers in NVIC	2018-03-08 09:34:37 -05:00
cpu.h	hw/intc/armv7m_nvic: Implement SCR	2018-03-08 09:36:59 -05:00
cpu64.c	target/arm: enable user-mode SHA-3, SM3, SM4 and SHA-512 instruction support	2018-03-07 08:58:43 -05:00
crypto_helper.c	target/arm: implement SM4 instructions	2018-03-07 08:57:53 -05:00
helper-a64.c
helper-a64.h
helper.c	target/arm: Implement writing to CONTROL_NS for v8M	2018-03-08 09:39:43 -05:00
helper.h	target/arm: implement SM4 instructions	2018-03-07 08:57:53 -05:00
internals.h	target/arm: Enforce access to ZCR_EL at translation	2018-03-08 09:17:33 -05:00
iwmmxt_helper.c
kvm-consts.h
Makefile.objs
neon_helper.c
op_addsub.h
op_helper.c	accel/tcg: add size paremeter in tlb_fill()	2018-03-06 10:56:34 -05:00
psci.c
translate-a64.c	target/arm: Handle SVE registers when using clear_vec_high	2018-03-08 09:32:33 -05:00
translate.c	target/arm/translate.c: Fix missing 'break' for TT insns	2018-03-07 11:45:39 -05:00
translate.h	target/arm: Add SVE state to TB->FLAGS	2018-03-07 11:44:32 -05:00
unicorn.h
unicorn_aarch64.c	unicorn/aarch64: Use qemu-provided helpers for accessing VFP/NEON/SIMD registers	2018-03-07 11:25:41 -05:00
unicorn_arm.c	unicorn/aarch64: Use qemu-provided helpers for accessing VFP/NEON/SIMD registers	2018-03-07 11:25:41 -05:00